Hardcoded barrier CSR address

[colluca]

Do not hardcode barrier CSR address, but get it from riscv-opcodes encoding.h.

snitch_cluster/sw/snRuntime/src/sync.h

Lines 57 to 60 in 8a020de

	/// Synchronize cores in a cluster with a hardware barrier
	inline void snrt_cluster_hw_barrier() {
	asm volatile("csrr x0, 0x7C2" ::: "memory");
	}