Initial DummyBoard

The very first DummyBoard: Xilinx APSoC
Example Design to deal with (will be removed once I'm done)
Example Project There are more Projects in this Repo (Hopefuly, this is not going to be copy & paste)

Parts

This is not the entire parts list.

APSoC: XC7Z020-2CLG400I (Xilinx link, check Datasheets and User Guides)

131€ APSoC CORTEX-A9 ARTIX-7 400BGA on digikey.ch
Compatibility:

• RAM: 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories

RAM:

Query on digikey.ch

Bus Functional Model

Giving a base idea on the APSoCs connections.

• JTAG:
  • Exposed through JTAG header
  • Maybe expose through miniUSB
• 2 SDIO:
  • None yet
• 2 Ethernet:
  • Exposed (both?)
• 2 USB Hosts:
  • Exposed / Hub
• 2 SPI:
  • None
• 2 I2C:
  • None
• 2 UART:
  • None

Banks (Check UG585 page 54: ch. 2.5.4)

500:

• MIO 00...08:
• MIO 09...16:

501:

• MIO 16...27: Ethernet 0
• MIO 28...39: USB 0
• MIO 40...45: SDIO 0 requires this location to be bootable
• MIO 46...51: SPI 1
• MIO 52...53:

PCB Manufacturing

Turns out that we need things!
Layer count: 12
Transmission lines: 2+ Minimum trace width: 89um