probe-rs info improvements & corrections

[bugadani]

According to the Cortex M23 reference manual, the processor has an FPB, not a BPU. This is sligthly interesting since the FPB's IDs are close enough to the M33's BPU, but I think we should remain consistent with the documentation.

That being said the M23/33 components are slightly off. The reference manual lists the following components for M23:

• SCS
• DWT
• FPB (corrected the name in this PR)
• ETM
• CTI (added in this PR)
• MTB (missing)

M33 also lists TPUI instead of MTB but I didn't go further than to note this.

---

The PR also prints more info about the devices.

ATSAMD51 before:

ARM Chip with debug port Default:
Debug Port: DPv1, DP Designer: ARM Ltd
├── 0 MemoryAP
│   └── ROM Table (Class 1)
│       └── ROM Table (Class 1)
│           ├── Cortex-M4 SCS   (Generic IP component)
│           │   └── CPUID
│           │       ├── IMPLEMENTER: ARM Ltd
│           │       ├── VARIANT: 0
│           │       ├── PARTNO: 3108
│           │       └── REVISION: 1
│           ├── Cortex-M3 DWT   (Generic IP component)
│           ├── Cortex-M3 FBP   (Generic IP component)
│           ├── Cortex-M3 ITM   (Generic IP component)
│           ├── Cortex-M4 TPIU  (Coresight Component)
│           ├── Cortex-M4 ETM   (Coresight Component)
│           └── CoreSight ETB   (Coresight Component)
└── 1 MemoryAP
    └── Error during access: Error using access port

ATSAMD51 after:

ARM Chip with debug port Default:
Debug Port: DPv1, DP Designer: ARM Ltd
├── 0 MemoryAP
│   └── Atmel DSU (ROM Table, Class 1)
│       ├── Atmel device (DID = 0x60060001
│       └── ROM Table (Class 1), Designer: ARM Ltd
│           ├── Cortex-M4 SCS   (Generic IP component)
│           │   └── CPUID
│           │       ├── IMPLEMENTER: ARM Ltd
│           │       ├── VARIANT: 0
│           │       ├── PARTNO: Cortex-M4
│           │       └── REVISION: 1
│           ├── Cortex-M3 DWT   (Generic IP component)
│           ├── Cortex-M3 FBP   (Generic IP component)
│           ├── Cortex-M3 ITM   (Generic IP component)
│           ├── Cortex-M4 TPIU  (Coresight Component)
│           ├── Cortex-M4 ETM   (Coresight Component)
│           └── CoreSight ETB   (Coresight Component)
└── 1 MemoryAP
    └── Error during access: Error using access port

ATSAML10 before:

ARM Chip with debug port Default:
Debug Port: DPv1, MINDP, DP Designer: ARM Ltd
└── 0 MemoryAP
    └── ROM Table (Class 1)
        └── ROM Table (Class 1)
            ├── Cortex-M23 SCS  (Coresight Component)
            ├── Cortex-M23 DWT  (Coresight Component)
            └── Cortex-M23 BPU  (Coresight Component)

ATSAML10 after:

ARM Chip with debug port Default:
Debug Port: DPv1, MINDP, DP Designer: ARM Ltd
└── 0 MemoryAP
    └── Atmel DSU (ROM Table, Class 1)
        ├── Atmel device (DID = 0x20840103)
        └── ROM Table (Class 1), Designer: ARM Ltd
            ├── Cortex-M23 SCS  (Coresight Component)
            │   └── CPUID
            │       ├── IMPLEMENTER: ARM Ltd
            │       ├── VARIANT: 1
            │       ├── PARTNO: Cortex-M23
            │       └── REVISION: 0
            ├── Cortex-M23 DWT  (Coresight Component)
            └── Cortex-M23 FBP  (Coresight Component)

[bugadani]

This PR went in a big circle. I ended up removing the half-baked part identification parts, I have a better idea how to approach that problem now.

[Yatekii]

This is the kind of thing I do not want :/ Special casing per chip in random places. It will deteriorate as quick as OpenOCD :/
Do we have any plans to make this more generic? I am not against special casing (we need it) but we should have a system for it where one can add any number of cases without littering the code. Similar to let's say a service router (not exactly like that ofc :D).

[bugadani]

Do we have any plans to make this more generic?

This isn't per chip, this is per manufacturer :) I hear your concern and we'll see what I can do here. I have plans for chip identification but that idea isn't very well integrated into the "parse random ROM tables and print their data" idea of info.

[Yatekii]

Ok :) I am fine with having this for now, but let's put emphasis on cleaning it up rather soon :)

[Yatekii]

Overall, I like this, thanks! I added some comments that are a bit more than nitpicks for me :)