Source code of the first assignment from the course Cryptographic Engineering, offered at Radboud University, handed out by Pedro Maat Costa Massolino.
The aim of this exercise is to get familiar with digital circuit design for the AES block cipher, written in VHDL.
The task is to optimize the key generation routine. This is done by generating keys on the fly, instead of having a memory that holds all round keys.
cd vhdl_source
make test_core
gtkwave tb_aes128_core.ghw