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Add aarch64 emulation #732
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For now I'm really just looking for confirmation that I'm in the right path. Do we want to revisit I can see life with qemu + gdb, but there's no output of any kind. Any suggestions on how to add proper PL011 support? There are some crates, but they depend on cortex-m. @orangecms FYI |
Failing due to lack of #728 |
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Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #732 +/- ##
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Coverage 0.21% 0.21%
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Files 22 22
Lines 938 938
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Hits 2 2
Misses 936 936 ☔ View full report in Codecov by Sentry. |
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Looks perfectly fine to me :) For QEMU, the approach from what I am thinking of would be to really just have the main stage and test the higher-level features - decompression, running some test payload, and seeing that our setup works fine (whatever it'd be on Arm, for RISC-V it'd be the SBI, etc). Does that make sense to you as well? If you don't mind, I'd love to take that first commit here already. Would you move that over into another PR? :) |
For the PL011, you can use the register block definition from here: just copy that over, essentially, and implement the embedded HAL trait for it and the oreboot log library: |
Signed-off-by: Felipe Balbi <felipe@balbi.sh>
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First we teach
xtask
how to compile RiscV emulation and proceed with re-addingqemu-aarch64
target.