generic: phy-mediatek-xfi-tphy: fix SGMII issue

Fix issue of transmitting abnormal data which leads to link problems in 1G and 2.5G SerDes modes (SGMII, 1000Base-X, 2500Base-X) on the MediaTek MT7988 SoC. Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/b72d6cba92bf9e29fb035c03052fa1e86664a25b Signed-off-by: Daniel Golle <daniel@makrotopia.org>
openwrt · Mar 25, 2024 · 79e9ce3 · 79e9ce3
1 parent 71ccb35
commit 79e9ce3
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Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch b/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
@@ -102,7 +102,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-mt2701.o
 --- /dev/null
 +++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
-@@ -0,0 +1,392 @@
+@@ -0,0 +1,393 @@
 +// SPDX-License-Identifier: GPL-2.0-or-later
 +/* MediaTek 10GE SerDes PHY driver
 + *
@@ -272,6 +272,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +			   XTP_PCS_PWD_ASYNC(2));
 +
 +	usleep_range(1, 5);
++	writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40);
 +
 +	/* Setup TX DA default value */
 +	mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);

diff --git a/target/linux/generic/pending-6.6/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch b/target/linux/generic/pending-6.6/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
@@ -102,7 +102,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-mt2701.o
 --- /dev/null
 +++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
-@@ -0,0 +1,392 @@
+@@ -0,0 +1,393 @@
 +// SPDX-License-Identifier: GPL-2.0-or-later
 +/* MediaTek 10GE SerDes PHY driver
 + *
@@ -272,6 +272,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +			   XTP_PCS_PWD_ASYNC(2));
 +
 +	usleep_range(1, 5);
++	writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40);
 +
 +	/* Setup TX DA default value */
 +	mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);