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x86: add support for 6.6 kernel version
Initial support for 6.6 kernel version Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,250 @@ | ||
| CONFIG_AR8216_PHY=y | ||
| CONFIG_ARCH_32BIT_OFF_T=y | ||
| CONFIG_ARCH_HIBERNATION_POSSIBLE=y | ||
| CONFIG_ARCH_KEEP_MEMBLOCK=y | ||
| CONFIG_ARCH_MMAP_RND_BITS_MAX=15 | ||
| CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 | ||
| CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| CONFIG_BLK_MQ_PCI=y | ||
| # CONFIG_CACHESTAT_SYSCALL is not set | ||
| CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" | ||
| CONFIG_CC_NO_ARRAY_BOUNDS=y | ||
| CONFIG_CEVT_R4K=y | ||
| CONFIG_CEVT_SYSTICK_QUIRK=y | ||
| CONFIG_CLKEVT_RT3352=y | ||
| CONFIG_CLKSRC_MMIO=y | ||
| CONFIG_CLK_MTMIPS=y | ||
| CONFIG_CLONE_BACKWARDS=y | ||
| CONFIG_CMDLINE="rootfstype=squashfs,jffs2" | ||
| CONFIG_CMDLINE_BOOL=y | ||
| # CONFIG_CMDLINE_OVERRIDE is not set | ||
| CONFIG_COMMON_CLK=y | ||
| CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 | ||
| CONFIG_COMPAT_32BIT_TIME=y | ||
| CONFIG_CPU_GENERIC_DUMP_TLB=y | ||
| CONFIG_CPU_HAS_DIEI=y | ||
| CONFIG_CPU_HAS_PREFETCH=y | ||
| CONFIG_CPU_HAS_RIXI=y | ||
| CONFIG_CPU_HAS_SYNC=y | ||
| CONFIG_CPU_LITTLE_ENDIAN=y | ||
| CONFIG_CPU_MIPS32=y | ||
| # CONFIG_CPU_MIPS32_R1 is not set | ||
| CONFIG_CPU_MIPS32_R2=y | ||
| CONFIG_CPU_MIPSR2=y | ||
| CONFIG_CPU_MIPSR2_IRQ_VI=y | ||
| CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y | ||
| CONFIG_CPU_R4K_CACHE_TLB=y | ||
| CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y | ||
| CONFIG_CPU_SUPPORTS_HIGHMEM=y | ||
| CONFIG_CPU_SUPPORTS_MSA=y | ||
| CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y | ||
| CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 | ||
| CONFIG_CRYPTO_LIB_SHA1=y | ||
| CONFIG_CRYPTO_LIB_UTILS=y | ||
| CONFIG_CRYPTO_RNG2=y | ||
| CONFIG_CSRC_R4K=y | ||
| CONFIG_DEBUG_INFO=y | ||
| CONFIG_DEBUG_INFO_COMPRESSED_NONE=y | ||
| # CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set | ||
| # CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set | ||
| CONFIG_DEBUG_PINCTRL=y | ||
| CONFIG_DMA_NONCOHERENT=y | ||
| # CONFIG_DMAPOOL_TEST is not set | ||
| # CONFIG_DTB_MT7620A_EVAL is not set | ||
| # CONFIG_DTB_OMEGA2P is not set | ||
| CONFIG_DTB_RT_NONE=y | ||
| # CONFIG_DTB_VOCORE2 is not set | ||
| CONFIG_DTC=y | ||
| CONFIG_EARLY_PRINTK=y | ||
| CONFIG_ETHERNET_PACKET_MANGLE=y | ||
| CONFIG_EXCLUSIVE_SYSTEM_RAM=y | ||
| CONFIG_FIXED_PHY=y | ||
| CONFIG_FWNODE_MDIO=y | ||
| # CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set | ||
| CONFIG_FW_LOADER_PAGED_BUF=y | ||
| CONFIG_FW_LOADER_SYSFS=y | ||
| CONFIG_GCC11_NO_ARRAY_BOUNDS=y | ||
| CONFIG_GENERIC_ATOMIC64=y | ||
| CONFIG_GENERIC_CLOCKEVENTS=y | ||
| CONFIG_GENERIC_CMOS_UPDATE=y | ||
| CONFIG_GENERIC_CPU_AUTOPROBE=y | ||
| CONFIG_GENERIC_GETTIMEOFDAY=y | ||
| CONFIG_GENERIC_IOMAP=y | ||
| CONFIG_GENERIC_IRQ_CHIP=y | ||
| CONFIG_GENERIC_IRQ_SHOW=y | ||
| CONFIG_GENERIC_LIB_ASHLDI3=y | ||
| CONFIG_GENERIC_LIB_ASHRDI3=y | ||
| CONFIG_GENERIC_LIB_CMPDI2=y | ||
| CONFIG_GENERIC_LIB_LSHRDI3=y | ||
| CONFIG_GENERIC_LIB_UCMPDI2=y | ||
| CONFIG_GENERIC_PCI_IOMAP=y | ||
| CONFIG_GENERIC_PHY=y | ||
| CONFIG_GENERIC_PINCONF=y | ||
| CONFIG_GENERIC_SCHED_CLOCK=y | ||
| CONFIG_GENERIC_SMP_IDLE_THREAD=y | ||
| CONFIG_GENERIC_TIME_VSYSCALL=y | ||
| CONFIG_GPIO_CDEV=y | ||
| # CONFIG_GPIO_LATCH is not set | ||
| # CONFIG_GPIO_MT7621 is not set | ||
| CONFIG_GPIO_RALINK=y | ||
| CONFIG_GPIO_WATCHDOG=y | ||
| # CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set | ||
| CONFIG_HARDWARE_WATCHPOINTS=y | ||
| CONFIG_HAS_DMA=y | ||
| CONFIG_HAS_IOMEM=y | ||
| CONFIG_HAS_IOPORT_MAP=y | ||
| CONFIG_HZ_PERIODIC=y | ||
| CONFIG_ICPLUS_PHY=y | ||
| # CONFIG_INGENIC_CGU_JZ4755 is not set | ||
| CONFIG_INITRAMFS_SOURCE="" | ||
| CONFIG_IRQCHIP=y | ||
| CONFIG_IRQ_DOMAIN=y | ||
| CONFIG_IRQ_FORCED_THREADING=y | ||
| CONFIG_IRQ_INTC=y | ||
| CONFIG_IRQ_MIPS_CPU=y | ||
| CONFIG_IRQ_WORK=y | ||
| # CONFIG_KALLSYMS_SELFTEST is not set | ||
| CONFIG_LIBFDT=y | ||
| # CONFIG_LEDS_GROUP_MULTICOLOR is not set | ||
| # CONFIG_LEGACY_TIOCSTI is not set | ||
| # CONFIG_LIST_HARDENED is not set | ||
| CONFIG_LOCK_DEBUGGING_SUPPORT=y | ||
| CONFIG_MARVELL_PHY=y | ||
| CONFIG_MAX_SKB_FRAGS=17 | ||
| CONFIG_MDIO_BUS=y | ||
| CONFIG_MDIO_DEVICE=y | ||
| CONFIG_MDIO_DEVRES=y | ||
| CONFIG_MEMFD_CREATE=y | ||
| CONFIG_MFD_SYSCON=y | ||
| # CONFIG_MFD_INTEL_M10_BMC_SPI is not set | ||
| # CONFIG_MFD_RK8XX_SPI is not set | ||
| # CONFIG_MFD_TPS6594_SPI is not set | ||
| CONFIG_MIGRATION=y | ||
| CONFIG_MIPS=y | ||
| CONFIG_MIPS_ASID_BITS=8 | ||
| CONFIG_MIPS_ASID_SHIFT=0 | ||
| CONFIG_MIPS_CLOCK_VSYSCALL=y | ||
| # CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set | ||
| # CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set | ||
| CONFIG_MIPS_CMDLINE_FROM_DTB=y | ||
| CONFIG_MIPS_L1_CACHE_SHIFT=5 | ||
| CONFIG_MIPS_LD_CAN_LINK_VDSO=y | ||
| # CONFIG_MIPS_NO_APPENDED_DTB is not set | ||
| CONFIG_MIPS_RAW_APPENDED_DTB=y | ||
| CONFIG_MIPS_SPRAM=y | ||
| # CONFIG_MODULE_DEBUG is not set | ||
| CONFIG_MODULES_USE_ELF_REL=y | ||
| # CONFIG_MT7621_WDT is not set | ||
| # CONFIG_MTD_CFI_INTELEXT is not set | ||
| CONFIG_MTD_CMDLINE_PARTS=y | ||
| # CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set | ||
| CONFIG_MTD_PHYSMAP=y | ||
| CONFIG_MTD_SPI_NOR=y | ||
| CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y | ||
| CONFIG_MTD_SPLIT_JIMAGE_FW=y | ||
| CONFIG_MTD_SPLIT_SEAMA_FW=y | ||
| CONFIG_MTD_SPLIT_TPLINK_FW=y | ||
| CONFIG_MTD_SPLIT_UIMAGE_FW=y | ||
| CONFIG_MTD_VIRT_CONCAT=y | ||
| CONFIG_NEED_DMA_MAP_STATE=y | ||
| CONFIG_NEED_PER_CPU_KM=y | ||
| CONFIG_NET_RALINK_GSW_MT7620=y | ||
| CONFIG_NET_RALINK_MDIO=y | ||
| CONFIG_NET_RALINK_MDIO_MT7620=y | ||
| CONFIG_NET_RALINK_MT7620=y | ||
| # CONFIG_NET_RALINK_RT3050 is not set | ||
| CONFIG_NET_RALINK_SOC=y | ||
| CONFIG_NET_SELFTESTS=y | ||
| # CONFIG_NET_VENDOR_MEDIATEK is not set | ||
| CONFIG_NET_VENDOR_RALINK=y | ||
| CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y | ||
| CONFIG_NVMEM=y | ||
| CONFIG_NVMEM_LAYOUTS=y | ||
| CONFIG_OF=y | ||
| CONFIG_OF_ADDRESS=y | ||
| CONFIG_OF_EARLY_FLATTREE=y | ||
| CONFIG_OF_FLATTREE=y | ||
| CONFIG_OF_GPIO=y | ||
| CONFIG_OF_IRQ=y | ||
| CONFIG_OF_KOBJ=y | ||
| CONFIG_OF_MDIO=y | ||
| # CONFIG_OVERLAY_FS_DEBUG is not set | ||
| CONFIG_PAGE_POOL=y | ||
| CONFIG_PAGE_SIZE_LESS_THAN_256KB=y | ||
| CONFIG_PAGE_SIZE_LESS_THAN_64KB=y | ||
| CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y | ||
| CONFIG_PCI=y | ||
| CONFIG_PCI_DOMAINS=y | ||
| CONFIG_PCI_DRIVERS_LEGACY=y | ||
| # CONFIG_PCI_DYNAMIC_OF_NODES is not set | ||
| CONFIG_PERF_USE_VMALLOC=y | ||
| CONFIG_PGTABLE_LEVELS=2 | ||
| CONFIG_PHYLIB=y | ||
| CONFIG_PHYLIB_LEDS=y | ||
| # CONFIG_PHY_MT7621_PCI is not set | ||
| CONFIG_PHY_RALINK_USB=y | ||
| CONFIG_PINCTRL=y | ||
| # CONFIG_PINCTRL_AW9523 is not set | ||
| CONFIG_PINCTRL_MT7620=y | ||
| # CONFIG_PINCTRL_MT76X8 is not set | ||
| CONFIG_PINCTRL_RALINK=y | ||
| # CONFIG_PINCTRL_SINGLE is not set | ||
| CONFIG_PREEMPT_NONE_BUILD=y | ||
| CONFIG_PTP_1588_CLOCK_OPTIONAL=y | ||
| CONFIG_RALINK=y | ||
| CONFIG_RALINK_WDT=y | ||
| # CONFIG_RANDOM_KMALLOC_CACHES is not set | ||
| CONFIG_RANDSTRUCT_NONE=y | ||
| CONFIG_RATIONAL=y | ||
| CONFIG_REGMAP=y | ||
| CONFIG_REGMAP_MMIO=y | ||
| CONFIG_RESET_CONTROLLER=y | ||
| # CONFIG_SERIAL_8250_PCI1XXXX is not set | ||
| CONFIG_SERIAL_8250_RT288X=y | ||
| CONFIG_SERIAL_MCTRL_GPIO=y | ||
| CONFIG_SERIAL_OF_PLATFORM=y | ||
| # CONFIG_SLAB_DEPRECATED is not set | ||
| # CONFIG_SLUB_TINY is not set | ||
| CONFIG_SOC_MT7620=y | ||
| # CONFIG_SOC_MT7621 is not set | ||
| # CONFIG_SOC_RT288X is not set | ||
| # CONFIG_SOC_RT305X is not set | ||
| # CONFIG_SOC_RT3883 is not set | ||
| CONFIG_SPI=y | ||
| CONFIG_SPI_MASTER=y | ||
| CONFIG_SPI_MEM=y | ||
| # CONFIG_SPI_MT7621 is not set | ||
| # CONFIG_SPI_PCI1XXXX is not set | ||
| CONFIG_SPI_RT2880=y | ||
| # CONFIG_SPI_SN_F_OSPI is not set | ||
| # CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set | ||
| # CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set | ||
| # CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set | ||
| CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y | ||
| CONFIG_SRCU=y | ||
| CONFIG_SWCONFIG=y | ||
| CONFIG_SWCONFIG_LEDS=y | ||
| CONFIG_SWPHY=y | ||
| CONFIG_SYSCTL_EXCEPTION_TRACE=y | ||
| CONFIG_SYS_HAS_CPU_MIPS32_R1=y | ||
| CONFIG_SYS_HAS_CPU_MIPS32_R2=y | ||
| CONFIG_SYS_HAS_EARLY_PRINTK=y | ||
| CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y | ||
| CONFIG_SYS_SUPPORTS_ARBIT_HZ=y | ||
| CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y | ||
| CONFIG_SYS_SUPPORTS_MIPS16=y | ||
| CONFIG_SYS_SUPPORTS_ZBOOT=y | ||
| CONFIG_TARGET_ISA_REV=2 | ||
| # CONFIG_TEST_DHRY is not set | ||
| CONFIG_TICK_CPU_ACCOUNTING=y | ||
| CONFIG_TIMER_OF=y | ||
| CONFIG_TIMER_PROBE=y | ||
| CONFIG_TINY_SRCU=y | ||
| # CONFIG_TMPFS_QUOTA is not set | ||
| CONFIG_USB_SUPPORT=y | ||
| CONFIG_USE_OF=y | ||
| # CONFIG_VCAP is not set | ||
| CONFIG_WATCHDOG_CORE=y | ||
| # CONFIG_WPCM450_SOC is not set | ||
| # CONFIG_WQ_CPU_INTENSIVE_REPORT is not set | ||
| CONFIG_ZBOOT_LOAD_ADDRESS=0x0 |
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...mips/patches-5.15/000-v5.18-01-dt-bindings-reset-add-dt-binding-header-for-Mediatek.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,60 @@ | ||
| From f383b0770612838e78986231710c0a3afee4db42 Mon Sep 17 00:00:00 2001 | ||
| From: Sergio Paracuellos <sergio.paracuellos@gmail.com> | ||
| Date: Mon, 10 Jan 2022 12:49:27 +0100 | ||
| Subject: [PATCH 1/2] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets | ||
| MIME-Version: 1.0 | ||
| Content-Type: text/plain; charset=UTF-8 | ||
| Content-Transfer-Encoding: 8bit | ||
|
|
||
| Add dt binding header for resets lines in Mediatek MT7621 SoCs. | ||
|
|
||
| Acked-by: Rob Herring <robh@kernel.org> | ||
| Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> | ||
| Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> | ||
| Link: https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com | ||
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | ||
| --- | ||
| include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++++++++++ | ||
| 1 file changed, 37 insertions(+) | ||
| create mode 100644 include/dt-bindings/reset/mt7621-reset.h | ||
|
|
||
| --- /dev/null | ||
| +++ b/include/dt-bindings/reset/mt7621-reset.h | ||
| @@ -0,0 +1,37 @@ | ||
| +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ | ||
| +/* | ||
| + * Copyright (c) 2021 Sergio Paracuellos | ||
| + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> | ||
| + */ | ||
| + | ||
| +#ifndef DT_BINDING_MT7621_RESET_H | ||
| +#define DT_BINDING_MT7621_RESET_H | ||
| + | ||
| +#define MT7621_RST_SYS 0 | ||
| +#define MT7621_RST_MCM 2 | ||
| +#define MT7621_RST_HSDMA 5 | ||
| +#define MT7621_RST_FE 6 | ||
| +#define MT7621_RST_SPDIFTX 7 | ||
| +#define MT7621_RST_TIMER 8 | ||
| +#define MT7621_RST_INT 9 | ||
| +#define MT7621_RST_MC 10 | ||
| +#define MT7621_RST_PCM 11 | ||
| +#define MT7621_RST_PIO 13 | ||
| +#define MT7621_RST_GDMA 14 | ||
| +#define MT7621_RST_NFI 15 | ||
| +#define MT7621_RST_I2C 16 | ||
| +#define MT7621_RST_I2S 17 | ||
| +#define MT7621_RST_SPI 18 | ||
| +#define MT7621_RST_UART1 19 | ||
| +#define MT7621_RST_UART2 20 | ||
| +#define MT7621_RST_UART3 21 | ||
| +#define MT7621_RST_ETH 23 | ||
| +#define MT7621_RST_PCIE0 24 | ||
| +#define MT7621_RST_PCIE1 25 | ||
| +#define MT7621_RST_PCIE2 26 | ||
| +#define MT7621_RST_AUX_STCK 28 | ||
| +#define MT7621_RST_CRYPTO 29 | ||
| +#define MT7621_RST_SDXC 30 | ||
| +#define MT7621_RST_PPE 31 | ||
| + | ||
| +#endif /* DT_BINDING_MT7621_RESET_H */ |
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