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mor1kx - an OpenRISC 1000 processor IP core
Verilog 472 145
Forked from bandvig/or1k_marocchino
OpenRISC processor IP core based on Tomasulo algorithm
Verilog 27 10
Misc documentation and specifications
10 10
Linux kernel source tree
glibc port for or1k
The OpenRISC 1000 architectural simulator
An verilog core for testing CPU interrupts
Source for openrisc.io
Unified OpenRISC 1000 test suite
GCC port for OpenRISC 1000
newlib OpenRISC development
Binutils and gdb fork for OpenRISC
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