TST: Add CPU Dispatch test for RISC-V Vector Extenson.

See #26219
numpy · Apr 17, 2024 · 30be005 · 30be005
1 parent 3c09f16
commit 30be005
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Showing 2 changed files with 17 additions and 1 deletion.
diff --git a/numpy/_core/tests/test_cpu_dispatcher.py b/numpy/_core/tests/test_cpu_dispatcher.py
@@ -12,7 +12,7 @@ def test_dispatcher():
         "SSE2", "SSE41", "AVX2",
         "VSX", "VSX2", "VSX3",
         "NEON", "ASIMD", "ASIMDHP",
-        "VX", "VXE"
+        "VX", "VXE", "RVV"
     )
     highest_sfx = "" # no suffix for the baseline
     all_sfx = []

diff --git a/numpy/_core/tests/test_cpu_features.py b/numpy/_core/tests/test_cpu_features.py
@@ -405,3 +405,19 @@ def load_flags(self):
                 # if the kernel reports any one of the following ARM8 features.
                 ASIMD=("AES", "SHA1", "SHA2", "PMULL", "CRC32")
             )
+
+is_riscv = re.match("^riscv(64|32)", machine, re.IGNORECASE)
+@pytest.mark.skipif(not is_linux or not is_riscv, reason="Only for Linux and RISC-V")
+class Test_RISCV_Features(AbstractTest):
+    features = ["RVV"]
+
+    def load_flags(self):
+        # self.load_flags_auxv()
+        isa = self.get_cpuinfo_item("isa")
+        is_vext = re.match("RV(64|32)[A-Z]*V[A-Z]*[A-Z,_]*", str(list(isa)[0]), re.IGNORECASE)
+        print(is_vext)
+        if(is_vext):
+            self.features_map = dict(
+                RVV="RVV"
+            )
+