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TST: Add CPU Dispatch test for RISC-V Vector Extenson. #3579

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TST: Add CPU Dispatch test for RISC-V Vector Extenson.

TST: Add CPU Dispatch test for RISC-V Vector Extenson. #3579

Triggered via pull request May 10, 2024 10:18
@ArielHelenetoArielHeleneto
synchronize #26300
ArielHeleneto:main
Status Cancelled
Total duration 11m 10s
Artifacts –

linux_simd.yml

on: pull_request
baseline_only
5m 59s
baseline_only
old_gcc
4m 42s
old_gcc
intel_sde_avx512
4m 43s
intel_sde_avx512
intel_sde_spr
4m 44s
intel_sde_spr
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9 errors
old_gcc
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
without optimizations
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
without avx512
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
intel_sde_spr
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
intel_sde_spr
The operation was canceled.
intel_sde_avx512
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
intel_sde_avx512
The operation was canceled.
native
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
without avx512/avx2/fma3
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists