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TST: Add CPU Dispatch test for RISC-V Vector Extenson. #3577

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TST: Add CPU Dispatch test for RISC-V Vector Extenson.

TST: Add CPU Dispatch test for RISC-V Vector Extenson. #3577

Triggered via pull request May 10, 2024 10:01
@ArielHelenetoArielHeleneto
synchronize #26300
ArielHeleneto:main
Status Cancelled
Total duration 13m 20s
Artifacts –

linux_simd.yml

on: pull_request
baseline_only
5m 57s
baseline_only
old_gcc
6m 59s
old_gcc
intel_sde_avx512
7m 0s
intel_sde_avx512
intel_sde_spr
7m 1s
intel_sde_spr
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6 errors
old_gcc
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
intel_sde_avx512
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
intel_sde_avx512
The operation was canceled.
without avx512
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
intel_sde_spr
Canceling since a higher priority waiting request for 'Linux SIMD tests-main' exists
intel_sde_spr
The operation was canceled.