Lemoncore is a simple RISC-V processor core targeting FPGAs. It implements the base RV32I instruction set, along with M-mode from the RISC-V privilege spec.
This repository contains the implementation of Lemoncore itself, along with a simple SoC implementation, automated tests, simulation code, and example software.
The easiest way to get started with Lemoncore is to run the SoC simulation.
The simulation requires installing the following dependencies:
Then, run make sim to run the simulator on the default firmware (sw/hello.c).
See below for more details on using the simulation, as well as instructions for running tests or building the SoC for an Icebreaker FPGA.
make sim-soc FW=<firmware>
Runs interactive SoC simulation. The simulator displays an ASCII representation
of the Icebreaker LEDs, and uses the keyboard for providing button input. Runs
sw/hello.c by default, but setting the optional FW variable will cause Make
to build sw/<firmware>.c and run that file instead.
You can also run the simulator executable directly. Run make socsim to compile
the binary, then ./socsim to run. Run ./socsim --help for more info on
command line configuration options.
make sim-core FW=<firmware>
Runs simulation of Lemoncore alone. This provides outputs as a trace of memory
reads/writes. The software to run can be selected via FW as in the SoC
simulation target.
make test
Runs all tests.
make test-core
make test-soc
make test-alu
make test-decoder
make test-ext
make test-regfile
Runs tests for the Lemoncore, SoC, or individual module (alu, decoder, ext, or regfile), respectively.
make
Builds bitstream of SoC targeting the Icebreaker.
make prog FW=<firmware>
Injects compiled sw/<firmware>.c into bitstream, and flashes it onto a connected FPGA using
iceprog.
SiliconCompiler:
pip install siliconcompiler
python lemoncore.py -remote
Builds Lemoncore ASIC using SiliconCompiler's cloud beta server.
RTL for Lemoncore CPU.
RTL for a simple SoC that incorporates Lemoncore, memory, a GPIO peripheral, and a timer module, targeting the Icebreaker FPGA.
Automated testbenches for Lemoncore, SoC, and individual modules that make up the core.
Simulation harnesses for the SoC and CPU.
Example software and a simple library that implements a code entry point and functions for interfacing with SoC peripherals.
This project is copyright 2020 Noah Moroze, released under the MIT license.