This project exposes the UART pins of the FT2232H on I/O pins 26 and 27 of the Digilent Arty development board.
To compile the design in Vivado
- Create a new project, select XC7A35TICSG324-1L as the FPGA
- Add
top.v
as a design source - Add
Arty_Master.xdc
as a constraint file - Generate Bitstream (Note, all the logic that’s necessary is already implemented!)
- Afterwards, you’ll get a top.bit file under your project folder under
<project name>.runs
andimpl_1
. - Use Vivado's Hardware Manager to load this bitstream on the FPGA.