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Pull requests: myhdl/myhdl

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Pull requests list

Removed support for Python 3.7 (which is End Of Life since 2023-06-27)
#430 opened Feb 22, 2024 by josyb Loading…
7
Add reverse updated to Github actions
#398 opened Dec 16, 2022 by davekeeshan Loading…
1
7
Fixes issue #388 incorrect conversion of elif siga == expression
#389 opened Dec 9, 2022 by josyb Loading…
1
3
Reduce memory footprint
#381 opened Oct 23, 2022 by telemarkguru Loading…
10
Added support for lists in ports
#362 opened Feb 24, 2022 by lucasasselli Loading…
5
Fix for issue #348 (traceSignals incorrectly writes real value signal to VCD)
#351 opened Dec 4, 2020 by NicoPy Loading…
1
Use first value instead of -1 as index in for loops
#347 opened Aug 31, 2020 by benzea Loading…
3
Added cosimulation with verilator v4 and https://github.com/csail-csg/pyverilator
#338 opened Apr 13, 2020 by joshuisken Loading…
3
Added test case for IfExp assigning to an intermediate
#330 opened Feb 16, 2020 by jdavidberger Loading…
block decorator parameterization and simpler signal names when needed
#328 opened Jan 20, 2020 by jvillar Loading…
Dynamic ports: allow kwargs in module interfaces
#327 opened Jan 16, 2020 by jvillar Loading…
1
Fix 316 literals have wrong size
#317 opened Jun 6, 2019 by jlusiardi Loading…
1
3
Enhanced ShadowSignals
#290 opened Dec 16, 2018 by josyb Loading… 0.12
@cfelton
6
EnumType is allowed as free variables
#260 opened Mar 24, 2018 by hashhsah Loading… 0.12
3
VHDL conversion : Add variable initialisation enhancement
#254 opened Feb 28, 2018 by NicoPy Loading… 0.12
15
draft of modified vpi module for cosimulation improvements
#221 opened Apr 26, 2017 by zhengfuli Loading…
1
Adding __reversed__ method
#207 opened Dec 13, 2016 by tokencolour Loading…
1
9
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