Verilog to bench converter

Based on the converter from NYU: https://github.com/NYU-Hardware-Security/Verilog-to-Bench

Converter for <Tsmc18_component, fast.db>

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DSD Lab @ University of Tehran, Iran

CompArch Group @ National University of Singapore, Singapore

Last modified by: Mona Hashemi hashemi.mona@ut.ac.ir, 2023

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Run

python3 tobench.py -i <INPUT_FILE> -o <OUTPUT_FILE>