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This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

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Buraq-Mini: An In-Order Fully Bypassed RISC-V Core

Buraq-Mini is a 5 stage pipelined processor which is made in Chisel from scratch and is used inside the "Ibtida SoC" which is selected for the first open-source ASIC tapeout in the Google + Efabless Open MPW Shuttle program.

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This repository standalone does not build. Check the decoupled-interface branch for more details on how to build the repository.

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This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

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