AES

FPGA Application

An Advanced Encryption Standard is an encryption algorithm for securing sensitive but unclassified material by U.S. Government agencies.

##Objectives Implemented in C++ and SystemVerilog on the FPGA board an encryption/decryption system that uses Altera's NIOS II embedded processor to coordinate data transfer between software and hardware.

##Details

Languages: C++, SystemVerilog
Environment: Altera Quartus II, ModelSim, NIOS II

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
AES.sv		AES.sv
AddRoundKey.sv		AddRoundKey.sv
InvMixColumns.sv		InvMixColumns.sv
InvShiftRows.sv		InvShiftRows.sv
InvSubByte.sv		InvSubByte.sv
KeyExpansion.sv		KeyExpansion.sv
README.md		README.md
Round1.sv		Round1.sv
Round2.sv		Round2.sv
Round3.sv		Round3.sv
Round4.sv		Round4.sv
Round5.sv		Round5.sv
Round6.sv		Round6.sv
Round7.sv		Round7.sv
Round8.sv		Round8.sv
Round9.sv		Round9.sv
Rounds.sv		Rounds.sv
SubBytes.sv		SubBytes.sv
aes_controller.sv		aes_controller.sv
lab9.sv		lab9.sv

matthewly/AES

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AES

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