CBx/CBy support input ports from grid outputs

[tangxifan]

Is your feature request related to a problem? Please describe.
Driven by the intensive needs on routing architecture, there is a trend that the feedback connections are moved to global routing, instead of local routing.
As a result, the feedback connections are merged into connection blocks, driving the routing multiplexers inside.

Describe the solution you'd like

VPR has already supported the routing architecture by using the existing syntax directlist.
See an example here

To be more specific, the direction connections can start and end at the same programmable block. See the example below:

    <direct name="LAB_self_sneak0" from_pin="LAB.data_out[0:0]" from_side="top" to_pin="LAB.data_in[0:0]" to_side="top" x_offset="0" y_offset="0" z_offset="0"/>
    <direct name="LAB_self_sneak1" from_pin="LAB.data_out[0:0]" from_side="top" to_pin="LAB.data_in[1:1]" to_side="top" x_offset="0" y_offset="0" z_offset="0"/>
    <direct name="LAB_self_sneak2" from_pin="LAB.data_out[3:1]" from_side="top" to_pin="LAB.data_in[4:2]" to_side="top" x_offset="0" y_offset="0" z_offset="0"/>

In such cases, the direct connections can no longer be treated a point-to-point connection, but another connection in CB.
Currently, OpenFPGA add these direct connections in the top-level module one by one.
This is due to that the direct connections can be very random, only applied to a small region or even 1 programmable block.
So, additional syntax should be applied or auto-detection should be enabled on such self-connections.

[tangxifan]

Some modification will be applied on the feature branch openfpga of vtr:

• Use the switch index from direct connection in architecture XML when building tileable rr graph

As a result, when building fabric, the direct connection will be handled in two ways

• For delayless switch, the direction connection will be added to the top-level module
• For connection block switch (must be same as the cb mux defined in VPR arch), the direct connection will be inside CB as part of routing multiplexers

[tangxifan]

In OpenFPGA's architecture description, a new attribute built_in_cb=<bool> should be added. This is to

• Identify that the direct connection is part of CB routing multiplexers. It should not be considered as point-to-point connections.

[tangxifan]

Restriction:

• Currently only support input/outputs on the bottom and right sides of programmable blocks
• Feedback connections from the same side of a programmable block is ok.

Will release a figure about the restrictions.