ql_memory_bank reading bitstream back

[mustafaarslan0]

I use ql_memory_bank shift_register configuration protocol with SRAM cells. SRAM cells have BL, WL and WLR pins as described in .

We need read enable signal for reading SRAM but I think WLR is overkill for this function. Wouldn't it be better if we use 1-bit wide read_enable signal (connected to all SRAMs) and WL together. WL is for decoding and read_enable signal is for deciding write or read operation.

Also BL should be defined as inout for bidirectional read/write operations.

Thank you,
Best regards.

[tangxifan]

@mustafaarslan0

In your case, you may consider to create a global signal EN for your SRAM.
Take the example (focus on the CFG_EN port)

https://openfpga.readthedocs.io/en/master/manual/arch_lang/circuit_model_examples/#configuration-chain-flip-flop-with-configure-enable-signals

[mustafaarslan0]

@tangxifan creating a global EN signal works. But BL should be defined as inout for bidirectional read/write operations.