LUT Internal Multiplexer: Custom Verilog File

[AidanJacobsen]

Open FGPA typically allows users to use a custom Verilog file using the verilog_netlist attribute.
As of now, it doesn't look like there is a way to use a custom netlist for the multiplexer that is
automatically generated within a LUT. This would be convenient so that when a multiplexer tree
is generated from standard cells, cells such as 4->1 multiplexers can be used through the inclusion
in a netlist file.

A workaround is to create a custom Verilog file for the whole netlist, but it would be convenient if just
the "lut_mux" module could be generated from a custom Verilog file while the full LUT module is still
automatically generated.

In the below image, I am showing my work-around where I am adding a netlist for the full lut. There is not
currently a spot to customize just the internal multiplexer's verilog description.