questions about a resource-efficient eFPGA design

[Chris202305]

I hope to minimize the usage of CLBs, SBs, and CBs in the eFPGA netlist, or in other words, use as few resources as possible. I've looked into the architecture file description, which primarily defines the structures of these modules. At which step should constraints be imposed on the quantity of these modules used in the generated netlist? Are there specific commands in VPR for this?