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Support LUTRAM mode in FPGA fabric #1471
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FYI, this is something we planned to do. I created the issue so that you can have early review. Please comment if you have any concern. |
I believe this is a good starting point to support LUTRAM.
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@chungshien @alaindargelas |
Hi @tangxifan Thanks for reviewing. Any other place to put this info? For us, we no longer use fabric_key.xml So if possible, I would like to avoid fabric_key.xml, but if you really think this is the ONLY BEST way to do so, then I will look into it. How about openfpga.xml
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I had moved the original XML code from VPR architecture XML (originally suggested by Dana) to Openfpga architecture XML (suggested by Xi Fan) I could see one extra benefit by doing so (even though the coding is more complex):
Latest code is committed into a branch via chungshien@df5ce25 Once PR #1566 is approved and merged, I could immediately PR to support this LUTRAM feature. One thing to note: Xi Fan is suggesting define the support in fabric_key.xml, which our company is no longer using it. So in my latest code, I am doing it in openfpga.xml (see my previous comment). Example of XML would be |
@ganeshgore for review too. |
We would like to support LUTRAM mode, where CLB can be configured to dual-port RAM.
This feaure uniquely exposes the structure of config bits to the customer, we need to enhance OpenFPGA so that customer's view align with OpenFPGA's.
Few changes are needed.
Change 1
For QL Memory Bank Flatten BL/WL configuration mode: fix the WL size for CLB tile to be 32bits. Existing OpenFPGA will try to keep BL and WL in a square shape if possible (with BL might be one bit bigger than WL in some cases)
Change 2
(I am middle to understand other changes, will update more)
Describe the solution you'd like
Change 1
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