Option to apply turbo bitstream loading in full testbenches for CCFF v2.0

[tangxifan]

Is your feature request related to a problem? Please describe.
In #1140 , the CCFF v2.0 allows users to define separated clocks on each configuration chain. Accordingly, the full testbench generator is upgraded to support the feature. In the full testbench, each programming clock is enabled for a fixed number of clock cycles, one after another. In such case, the simulation will take a long run. For example, there are 8 programming clocks and each clock controls 2k configuration bits. Then, 8x2 = 16k clock cycles are required to accomplish programming.

In practice, some turbo mode may be applied. For instance, users may start a few programming blocks at the same time, to reduce the time required for bitstream downloading.
Therefore, a new feature is required to customize the turbo mode for CCFF v2.0 w.r.t. testbench generators.

Describe the solution you'd like

Some new syntax should be added the openfpga simulation setting file

The configuration file will be in XML file format

<programming frequency="50MHz">
      <turbo_mode>
        <phase id ="0" port="prog_clk[0:3]"/>
        <phase id ="1" port="prog_clk[4:7]"/>
      </turbo_mode>
</programming>

[tangxifan]

Other bugs to be fixed:

The config enable should follow the last bit of config_done

reg [0:7] __config_done__;
assign config_enable[0] = __config_done__[0]; #	-> assign config_enable[0] = __config_done__[7]
always @(negedge __prog_clock___reg__[0]) begin # -> always @(negedge __prog_clock___reg__[5]) begin
	if (bit_index5 >= `BITSTREAM_LENGTH5) begin
		__config_done__[5] <= 1'b1;
	end else if (__config_done__[4] == 1'b1 && bit_index5 >= 0 && bit_index5 < `BITSTREAM_LENGTH5) begin
		ccff_head[0:31] <= bit_mem[bit_index5];
		bit_index5 <= bit_index5 + 1;
	end
end