Arterytek's AT32F4 support #1445

beefdeadbeef · 2022-11-09T21:11:42Z

Hi. I'm currently amusing myself with at32f403a based blackpill board --
you probably heard of those, stm32f10x frankenclone with m4f core, richer peripheral set,
flash shadowed by SRAM (no wait states!) and overally more of it.
Problem is, it's frankenclone in denial -- they renamed any and every register and bit name
in their docs, although maintaining very close compatibility at register level.
So, i'm curious, if is this approach with hijacking stm32f1 code base is acceptable at all (thus RFC) ?
Currently i have only basic things like rcc & flash, gpio and timers, enough for blinky with systick and timer (at 240Mhz wow).

karlp · 2022-11-09T21:59:08Z

include/libopencm3/at32/f4/memorymap.h

+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>


if you want a more favourable beginning, don't do things like this...

Oh sorry about that. Hadn't better idea how to attribute almost copypaste.

karlp · 2022-11-09T21:59:59Z

include/libopencm3/stm32/f1/rcc.h

+#define RCC_CFGR3				MMIO32(RCC_BASE + 0x30) /*(^^)*/
+#define RCC_CFGR4				MMIO32(RCC_BASE + 0x50) /*(^^)*/
+#define RCC_CFGR5				MMIO32(RCC_BASE + 0x54) /*(^^)*/
+#define RCC_CFGR6				MMIO32(RCC_BASE + 0x5c) /*(^^)*/


yeah, so, I'm not going personally merge anything that adds f1 registers for a different target and a different family. There's got to be a better way.

ifdef'ing those counts for (slightly) better way ?

I'm not sure honestly, the two approaches people have tried to take so far have largely been "copy paste the entire f1 tree" which is a maintenance nightmare, and "ifdef f1 code to be a trashfire supporting everything in the world" I imagine breaking it all into much smaller pieces so it can be composed more freely is likely the path forwards, but I've not tried (and it's not remotely on my own personal roadmap)

beefdeadbeef · 2022-11-13T21:05:20Z

So, another attempt. This time i've decided to let stm32f1 rcc code alone, let's see how this helps me.

karlp · 2022-12-05T10:48:03Z

include/libopencm3/at32/f40x/memorymap.h

+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>


I'm still not convinced Uwe has any copyright on this file. it's just header definitions from the datasheet. it's not "copying" when there's no other way? I'd go as far as saying there's not really any plausible copyright at all on this, as per oracle vs sco, but IANAL.

karlp · 2022-12-05T10:51:14Z

lib/at32/f40x/gpio.c

+@author @htmlonly &copy; @endhtmlonly 2012
+Ken Sarkies <ksarkies@internode.on.net>
+@author @htmlonly &copy; @endhtmlonly 2022
+Sergey Bolshakov <beefdeadbeef@gmail.com>


copyrights here don't match what you've got lower down, and isn't this all your own work? pretty sure there's nothing left of the 2009 code.

there's slightly modified (from f1 variant) gpio_set_mode(), unmodified gpio_set_eventout() and new gpio_set_mux().
git blame shows few lines exactly from 2009 by Uwe. But honestly all this copyright stuff isn't my idea of fun,
i'll gladly agree with what you see appropriate here.

karlp · 2022-12-05T10:53:01Z

lib/at32/f40x/rcc.c

+
+		/* Choose HSE as the RTC clock source. */
+		RCC_BDCR &= ~((1 << 8) | (1 << 9));
+		RCC_BDCR |= (1 << 9) | (1 << 8);


using different orders here was confusing and made me think you had a bug here :|

it survived that way from original submission in 2014, it seems. another wtf moment

karlp · 2022-12-05T10:54:40Z

I think this style looks a lot better personally!

beefdeadbeef · 2022-12-05T19:46:38Z

I think this style looks a lot better personally!

thanks. next in my todo list are usb with clock recovery, maybe flash bits.
oh, and could you please pick [db9f4ed] alone ? i2c code here depends on it.

karlp · 2022-12-06T12:47:31Z

Ify ou want standalone commits reviewed, make them a standalone PR please.

karlp · 2022-12-13T09:09:35Z

include/libopencm3/at32/f40x/memorymap.h

-#define USART7_BASE         (PERIPH_BASE_APB2 + 0x6400)
-#define USART8_BASE         (PERIPH_BASE_APB2 + 0x6800)
-#define I2S2_EXT_BASE       (PERIPH_BASE_APB2 + 0x6c00)
-#define I2S3_EXT_BASE       (PERIPH_BASE_APB2 + 0x7000)


it would be really nice not to have fixup commits in the same stack please. It makes splitting and bisection on a long set like this awful.

i'm planning to squash this commit with first in series anyway -- if that's okay.

karlp · 2022-12-13T09:10:50Z

include/libopencm3/at32/f40x/rcc.h

@@ -59,7 +59,7 @@
 #define RCC_CFGR3		MMIO32(RCC_BASE + 0x30)		/* CRM_MISC1 */
 #define RCC_CFGR4		MMIO32(RCC_BASE + 0x50)		/* CRM_MISC2 */
 #define RCC_CFGR5		MMIO32(RCC_BASE + 0x54)		/* CRM_MISC3 */
-#define RCC_INTMAP		MMIO32(RCC_BASE + 0x5c)		/* CRM_INTMAP */
+#define RCC_CFGR6		MMIO32(RCC_BASE + 0x5c)		/* CRM_INTMAP */


Is this defines to be compatible with stm32, but with comments (that no-one will ever see) showing what the actual vendor names are? I'm inclined to say you want them both defined in that case honestly.

well, that's about two dosens registers, which do not exist in stm32f1 -- making them just as they are in at32 docs
feels sometimes really meh. This particular diff just fixes difference in register naming with register value define for this register below.
And by the way comments like these are wisible in doxygen, no ?

karlp · 2022-12-13T09:12:06Z

lib/at32/f40x/rcc.c

 */

-void rcc_set_hsi_bypass(bool bypass)
+void rcc_set_hsi_div(uint32_t hsidiv)


was this just copypasta before? This sort of fixup is exactly what you don't want in unrelated changesets

no, that's was newly added. later i've decided that function naming doesn't follow existing pattern.
as i said, i'd like to squash this with initial commit later.

AT32F4 is a family of Cortex-M4/M4F MCUs made by Artery Technology. Their *Main Stream* series, which can be described as pumped STM32F1, includes AT32F40X/AT32F45X chips and features M4F core up to 240MHz, richer periheral set, shadowed flash with zero wait states and more, while tries to be compatible with original at register level. For now, add most basic things: * devices data * interrupt vectors * memory map

RCC on AT32F40x is similar with STM32F1x series, notable differences are (among others): * HSE clock in range 4-25 MHz * PLL multiplier up to 64x * HSI clock 48 MHz, which can be fed to USB * MCO output divider, down to /512

In addition to STM32F1 series AT32F40x features extra CAN2, SPI1/I2S, SPI4, SDIO2, I2C3, U(S)ART[6-8] etc, thus requiring more flexible pin muxer; in particular, eight MAPRx registers. Other notable difference, MAPR SWJ bits are just usual rw ones. On top of that, GPIO_MODE_OUTPUT_50_MHZ needs extra register poking. So, another piece of unique (sigh) API.

Timers on AT32F40x are mostly just as usual STM32 ones, with one notable addition: TIM[2-5] can be switched to 32-bit mode, namely TIMx_CNT, TIMx_ARR and TIMx_CCR[1-4] registers.

In addition to STM32F1 DMA controllers fuctionality, AT32F4x has so-called flexible request mapping mode, resembling channel remapping feature found on F0 MCUs, although implemented differently. Add support for it.

Add support for ADC, DAC, CAN, EXTI, I2C, IWDG, PWR, RTC, SPI and USART by reusing corresponding STM32F1 code.

in preparation for usbfs support, add * usbfs alternate packet memory selector * usbfs alternate interrupt vector selector. while not exactly reset and clock controls, they reside in RCC register space.

In addition to STM32F1 USBFS, AT32F40x has extra packet buffer, up to 1280 bytes in size, which can be selected instead of standard 512 bytes' one.

AT32F40x contains auto clock calibration block, which uses USB SOF signal as reference for HSI oscillator calibration. Add support for it by reusing CRS API.

AT32F4 is a family of Cortex-M4/M4F MCUs made by Artery Technology. Their *Value Line* series includes, among others, AT32F421/425 chips. Add basic support for those.

Add support for ADC, CRS, EXTI, I2C, IWDG, PWR, RTC, SPI TIM and USART by reusing corresponding STM32 code.

OTG_FS controller on AT32F425 is similar with one found in STM32, although it needs modified initialization procedure, in particular, device mode should be forced before powering up phy. Also, in contrary with documentation [RM_AT32F425_EN_V2.02], actual chips have OTG_FS_CID 0x2000, thus requiring PR#1261 [libopencm3#1261].

V2.04 and earlier of Artery's AT403A/407 Reference Manual sect 7.4.9 specifies b'0001' value for CH1/PB4 CH2/PB5 CH3/PB0 CH4/PB1 TIM3 pinmux. Actual hardware tests shows b'0010' should be used instead.

karlp reviewed Nov 9, 2022

View reviewed changes

beefdeadbeef force-pushed the at32f4 branch from 000b4d2 to 463267f Compare November 13, 2022 20:58

beefdeadbeef force-pushed the at32f4 branch from 463267f to f9592fe Compare November 25, 2022 21:40

karlp reviewed Dec 5, 2022

View reviewed changes

karlp reviewed Dec 13, 2022

View reviewed changes

beefdeadbeef force-pushed the at32f4 branch from 526b39e to 992e6f4 Compare December 13, 2022 20:50

beefdeadbeef changed the title ~~[RFC] Arterytek's AT32F4 support~~ Arterytek's AT32F4 support Dec 26, 2022

beefdeadbeef force-pushed the at32f4 branch from 992e6f4 to 2e4f198 Compare February 23, 2023 13:57

beefdeadbeef added 13 commits June 3, 2023 20:07

at32f40x: add rcc bits

a4f4683

RCC on AT32F40x is similar with STM32F1x series, notable differences are (among others): * HSE clock in range 4-25 MHz * PLL multiplier up to 64x * HSI clock 48 MHz, which can be fed to USB * MCO output divider, down to /512

at32f40x: add timers

de00236

Timers on AT32F40x are mostly just as usual STM32 ones, with one notable addition: TIM[2-5] can be switched to 32-bit mode, namely TIMx_CNT, TIMx_ARR and TIMx_CCR[1-4] registers.

at32f40x: add dma support

34906fe

In addition to STM32F1 DMA controllers fuctionality, AT32F4x has so-called flexible request mapping mode, resembling channel remapping feature found on F0 MCUs, although implemented differently. Add support for it.

stm32: ic2-v1: parametrize I2C_CR2_FREQ_MASK

070530d

at32f40x: add support for rest of peripherals

6945e88

Add support for ADC, DAC, CAN, EXTI, I2C, IWDG, PWR, RTC, SPI and USART by reusing corresponding STM32F1 code.

at32f40x: add usb related rcc bits

76a9932

in preparation for usbfs support, add * usbfs alternate packet memory selector * usbfs alternate interrupt vector selector. while not exactly reset and clock controls, they reside in RCC register space.

at32f40x: add usbfs support

dc533fe

In addition to STM32F1 USBFS, AT32F40x has extra packet buffer, up to 1280 bytes in size, which can be selected instead of standard 512 bytes' one.

at32f40x: usbfs: add gadget-zero test bits

5994a80

at32f40x: add hsi clock recovery

bf6d72c

AT32F40x contains auto clock calibration block, which uses USB SOF signal as reference for HSI oscillator calibration. Add support for it by reusing CRS API.

at32f4: rcc: split out common part

70be38a

at32f4: dma: split out common part

83df02b

beefdeadbeef added 11 commits June 3, 2023 20:45

at32f4: crs: split out common part

01a61b4

at32f4: timer: split out common part

0495bc3

at32f42x: initial support

e4f0f91

AT32F4 is a family of Cortex-M4/M4F MCUs made by Artery Technology. Their *Value Line* series includes, among others, AT32F421/425 chips. Add basic support for those.

at32f42x: add rcc bits

eb52ef3

at32f42x: add flash bits

aa2c5dd

at32f42x: add syscfg bits

03243f4

at32f42x: add gpio bits

895b2e4

at32f42x: add dma bits

dfb5ebc

at32f42x: add support for the rest of peripherals

040ce9f

Add support for ADC, CRS, EXTI, I2C, IWDG, PWR, RTC, SPI TIM and USART by reusing corresponding STM32 code.

at32f42x: otgfs: add gadget-zero test

8794f9d

beefdeadbeef force-pushed the at32f4 branch from 2e4f198 to 8794f9d Compare June 3, 2023 18:06

beefdeadbeef added 4 commits June 13, 2023 15:41

at32f42x: dma: fix TIM1_UP request

5006e7a

at32f40x: gpio: fix TIM3 pinmux

86ac31a

V2.04 and earlier of Artery's AT403A/407 Reference Manual sect 7.4.9 specifies b'0001' value for CH1/PB4 CH2/PB5 CH3/PB0 CH4/PB1 TIM3 pinmux. Actual hardware tests shows b'0010' should be used instead.

at32f4: rcc: split out common part

87d5348

at32f42x: rcc: add fractional mode PLL setup

0485b8f

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Arterytek's AT32F4 support #1445

Arterytek's AT32F4 support #1445

beefdeadbeef commented Nov 9, 2022

karlp Nov 9, 2022

beefdeadbeef Nov 9, 2022

karlp Nov 9, 2022

beefdeadbeef Nov 9, 2022

karlp Nov 10, 2022

beefdeadbeef commented Nov 13, 2022 •

edited

karlp Dec 5, 2022

karlp Dec 5, 2022

beefdeadbeef Dec 5, 2022

karlp Dec 5, 2022

beefdeadbeef Dec 5, 2022

karlp commented Dec 5, 2022

beefdeadbeef commented Dec 5, 2022

karlp commented Dec 6, 2022

karlp Dec 13, 2022

beefdeadbeef Dec 13, 2022

karlp Dec 13, 2022

beefdeadbeef Dec 13, 2022

karlp Dec 13, 2022

beefdeadbeef Dec 13, 2022

Arterytek's AT32F4 support #1445

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Arterytek's AT32F4 support #1445

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beefdeadbeef commented Nov 13, 2022 • edited

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karlp commented Dec 5, 2022

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beefdeadbeef commented Nov 13, 2022 •

edited