Jackson's Additional Steps:

Building:

• Get nix (https://nixos.org/)
• nix-shell # fetches dependencies
• mkdir build && cd build
• cmake ..
• make

Running example:

• cd test
• vim kernel.cpp # edit the loop to contain whatever.
• ./compile.sh, generate LLVM bitcode for that loop.
• ./run.sh --build # builds a cgra for that loop.
• ./build_param.sh operations.json # build the settings file for this new loop.
• ./run.sh # bulid for the CGRA that you just defined --- this should work
• vim kernel.cpp # edit this again to change it
• ./run.sh # without build, tries to compile the loop to that particular cgra configuration.
• ./run.sh --use-egraphs # use the egraphs rewriter
• ./run.sh --rewriter # use the traditioanl rewriter.
• Apply some rewrite rules by hand and try and make it work :)

#Running tests against a single cgra

• git clone git@github.com:j-c-w/LoopBenchmarks

• /run_tests_against.sh --use-egraphs

• /run_tests_against.sh

• should be a C file within Loop Benchmarks (e.g. ../../LoopBenchmarks/ll_loops/loops/loop10.c )

• should be the parent directory of the LoopBenchmarks repo

• Outputs are left in run_output.old

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/ /__/ (_ / , _/ __ |  / /|_/ / _ `/ _ \/ _ \/ -_) __/
\___/\___/_/|_/_/ |_| /_/  /_/\_,_/ .__/ .__/\__/_/   
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(Cloned from https://github.com/tancheng/CGRA-Mapper)

This is a CGRA (Coarse-Grained Reconfigurable Architecture) mapper to map the target loops onto the CGRA. The CGRA is parameterizable (e.g., CGRA size, type of the computing units in each tile, communication connection, etc.). Different advanced mapping strategies are built on top of this basic mapper. CGRA Mapper currently provides following features and functionalities:

• It takes the arch&kernel info in JSON format.
• It can generate the DFG/CDFG of the target code region (in .png).
• Nested-loop and complex if/else control flows are supported with partial predication.
• Users can easily invoke loop-unrolling in the compile/run script (opt --loop-unroll --unroll-count=4 -load PATH/libmapperPass.so -mapperPass kernel.bc).
• It schedules and maps the DFG onto the CGRA arch that is represented in MRRG.
• The generated dfg.json and config.json can be taken as inputs for the simulation in the OpenCGRA (register index needed to be manually added/distinguished).
• Benchmark including a set of representative kernels/applications with compilation scripts can be found here.

Showcase

// target FIR kernel
for (i = 0; i < NTAPS; ++i) {
    sum += input[i] * coefficient[i];
}

Citation

@inproceedings{tan2020opencgra,
  title={OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAs},
  author={Tan, Cheng and Xie, Chenhao and Li, Ang and Barker, Kevin J and Tumeo, Antonino},
  booktitle={2020 IEEE 38th International Conference on Computer Design (ICCD)},
  pages={381--388},
  year={2020},
  organization={IEEE}
}

License

CGRA-Mapper is offered under the terms of the Open Source Initiative BSD 3-Clause License. More information about this license can be found here:

• http://choosealicense.com/licenses/bsd-3-clause
• http://opensource.org/licenses/BSD-3-Clause

Build

The mapper requires the following additional prerequisites:

• LLVM 4.0 ~ LLVM 12.0
• CMAKE 3.1

Execution

• The pass should be built and run with the same version of the LLVM.

• A param.json indicating the configuration of the target CGRA and the kernel should locate in the kernel folder.

  • The kernel name in the param.json should be identical as the function name shown in the generated IR file. Note that different versions of LLVM could lead to different generated function names, which should be explicitly indicated in the param.json by the users.

• Run:

 % opt -load ~/this repo/build/mapper/libmapperPass.so -mapperPass ~/target benchmark/target_kernel.bc

Related publications

• Cheng Tan, et al. “DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications.” The 39th IEEE International Conference on Computer Design. (ICCD'21), Oct 2021.
• Cheng Tan, et al. “OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays.” The 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'21), A Virtual Conference, July 7-8, 2021.
• Cheng Tan, et al. "ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing." IEEE Transactions on Parallel and Distributed Systems (TPDS'21).
• Cheng Tan, et al. “AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators.” The 2021 Design, Automation & Test in Europe Conference, Grenoble, France. (DATE'21) February 1-5, 2021.
• Christopher Torng, et al. "Ultra-Elastic CGRAs for Irregular Loop Specialization." 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA'21).