Incorrect stack adjustment size when decoding "push r16" in x86 (32bit) mode

[xusheng6]

For instruciton "push bx" (6653), when xed decodes it in 32bit mode, the stack adjustment is reported as 32bits (4 bytes).

See ASZ0=32 in the following output:

$ obj/wkit/examples/obj/xed-ex1 6653
Attempting to decode: 66 53 
iclass PUSH	category PUSH	ISA-extension BASE	ISA-set I86
instruction-length 2
operand-width 16
effective-operand-width 16
effective-address-width 32
stack-address-width 32
iform-enum-name PUSH_GPRv_50
iform-enum-name-dispatch (zero based) 4
iclass-max-iform-dispatch 11
Nominal opcode position 1
Nominal opcode 0x53
Operands
#   TYPE               DETAILS        VIS  RW       OC2 BITS BYTES NELEM ELEMSZ   ELEMTYPE   REGCLASS
#   ====               =======        ===  ==       === ==== ===== ===== ======   ========   ========
0   REG0               REG0=BX   EXPLICIT   R         V   16     2     1     16        INT        GPR
1   REG1        REG1=STACKPUSH SUPPRESSED  RW       SPW   16     2     1     16        INT     PSEUDO
2   MEM0           (see below) SUPPRESSED   W       SPW   16     2     1     16        INT    INVALID
3  BASE0             BASE0=ESP SUPPRESSED  RW       SSZ   32     4     1     32        INT        GPR
Memory Operands
  0 written SEG= SS BASE= ESP/GPR  ASZ0=32
  MemopBytes = 2
ATTRIBUTES: FIXED_BASE0 SCALABLE STACKPUSH0 
66-OSZ PREFIX
ANY 66 PREFIX
Number of legacy prefixes: 1 
ISA SET: [I86]

However, this is wrong. I used a debugger to verify the stack adjustment is actually 2 bytes, not 4 bytes. This is now causing the downstream lifting error in the Binary NInja x86 arch plugin: Vector35/binaryninja-api#4028.

FYI, this is how we are handling the lifting of the push instruction: https://github.com/Vector35/arch-x86/blob/ce54c270537a36255608cd1f67df64f971558d0e/il.cpp#L2829-L2844. xed_decoded_inst_get_memop_address_width is reporting 32 where I believe it should return 16