GitHub - hasithvm/subleq-verilog: SUBLEQ implementation and testbenches.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commits
iseconfig		iseconfig
README		README
README~		README~
alu.cmd_log		alu.cmd_log
alu.jhd		alu.jhd
alu.sch		alu.sch
alu.sym		alu.sym
basicram.mem		basicram.mem
basicrom.mem		basicrom.mem
default_probe_Allthethings.wcfg		default_probe_Allthethings.wcfg
dp_ram.sym		dp_ram.sym
dp_ram.v		dp_ram.v
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
input_output_ports.sym		input_output_ports.sym
input_output_ports.v		input_output_ports.v
ireg_24.cmd_log		ireg_24.cmd_log
ireg_24.sym		ireg_24.sym
ireg_24.v		ireg_24.v
isim.log		isim.log
mux_2x1.cmd_log		mux_2x1.cmd_log
mux_2x1.spl		mux_2x1.spl
mux_2x1.sym		mux_2x1.sym
mux_2x1.v		mux_2x1.v
pc_incrementer.cmd_log		pc_incrementer.cmd_log
pc_incrementer.spl		pc_incrementer.spl
pc_incrementer.sym		pc_incrementer.sym
pc_incrementer.tfi		pc_incrementer.tfi
pc_incrementer.v		pc_incrementer.v
pc_reg.cmd_log		pc_reg.cmd_log
pc_reg.sym		pc_reg.sym
pc_reg.v		pc_reg.v
pc_reg_stx_beh.prj		pc_reg_stx_beh.prj
rom_256.sym		rom_256.sym
rom_256.v		rom_256.v
sch2HdlBatchFile		sch2HdlBatchFile
sequencer.cmd_log		sequencer.cmd_log
sequencer.jhd		sequencer.jhd
sequencer.sch		sequencer.sch
sequencer.sym		sequencer.sym
subleq_core.jhd		subleq_core.jhd
subleq_core.sch		subleq_core.sch
subleq_core.sym		subleq_core.sym
subleq_core_summary.html		subleq_core_summary.html
subleqr2.gise		subleqr2.gise
subleqr2.xise		subleqr2.xise
vff_input_output_ports.v		vff_input_output_ports.v
vtf_ir.v		vtf_ir.v
vtf_rom.v		vtf_rom.v
vtf_sequencer.v		vtf_sequencer.v
vtf_subleq_Core.v		vtf_subleq_Core.v

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Hi there!

If you're ever here, I'm assuming you know what you're doing. This project is licensed CreativeCommons-Attribution, so go ahead and use away, but drop me an email if you like what I do.

--Hasith Vidanamadura,
2012/03/18 18:42-0500