Simple-RISC-Machine

Finite state machine controlled reduced instruction set computing machine. Simulated using ModelSim and synthesized with Quartus II. Simulated on the DE1-SoC (Cyclone V FPGA).

Name		Name	Last commit message	Last commit date
Latest commit History 22 Commits
ALU testbench		ALU testbench
Arithmetic Logic Unit		Arithmetic Logic Unit
CPU testbench		CPU testbench
Central Processing Unit		Central Processing Unit
Datapath		Datapath
Datapath testbench		Datapath testbench
Decoder		Decoder
Decoder testbench		Decoder testbench
FSM Controller testbench		FSM Controller testbench
Finite State Machine Controller		Finite State Machine Controller
LED DE1-SoC Display		LED DE1-SoC Display
README.md		README.md
Register File		Register File
Register File testbench		Register File testbench
Shifter		Shifter
Shifter testbench		Shifter testbench
Stage 1		Stage 1
Stage 1 testbench		Stage 1 testbench

hannahvsawiuk/Simple-RISC-Machine

Folders and files

Latest commit

History

Repository files navigation

Simple-RISC-Machine

About

Topics

Resources

Stars

Watchers

Forks