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[Draft] CodeGen_MLIR: Add initial MLIR CodeGen #7587

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xerpi
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@xerpi xerpi commented May 21, 2023

Initial implementation. Just a proof-of-concept to show that MLIR generation is possible and quite straightforward.
It uses the following MLIR dialects: arith, func, memref, scf, vector.

Future work:

  • Implement the rest of the Halide IR node conversion
  • Use MLIR's affine dialect instead of scf's if, for, and memory load/stores to take advantage of affine transformations and optimizations.

@xerpi xerpi force-pushed the initial-mlir-codegen branch 4 times, most recently from cbc1a0b to 129964e Compare May 21, 2023 02:17
@xerpi xerpi marked this pull request as draft May 21, 2023 02:17
@zvookin
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zvookin commented May 21, 2023

I look forward to reading the PR and will try to do so soon.

MLIR definitely now has enough prebuilt dialect support to be able to support Halide well. The main issue for re: adding MLIR support in main is that it adds a significantly large dependency to the build. This has a cost on CI/testing.

The main advantage of MLIR would be as a fairly configurable backend to target a broad variety of dialects flexibly, specifically ML operation sets that end up on TPU hardware and such.

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zvookin commented May 21, 2023

I would like to see a quick readme with minimal info on how you set up/installed MLIR and possibly a shell script that generates something through this path and compiles it with mlir-opt or similar.

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xerpi commented May 24, 2023

@zvookin I have updated the pull request.

I have added compile_to_mlir methods to Func and Pipeline, which I'm not sure it's a good idea. What should be the behavior when Halide is compiled without MLIR, to return an error?

In my project, I use MLIR and CIRCT to generate generic RTL code which I wrap with Xilinx-specific wrappers, and I have also implemented a Halide runtime (xrt.cpp) for Xilinx Runtime Library (XRT) to interface with the FPGA device (allocate/deallocate memory, copy data device<->host and run kernel).
For that use case, I treat the FPGA as an "accelerator": I have a custom class OffloadLoopsToAccelerator which just marks loops to be executed on the FPGA (similarly to OffloadGPULoops) and calls the MLIR CodeGen to generate the MLIR code and replaces the loop execution to calls to the XRT runtime backend.

In the code in this pull request, when CodeGen_MLIR is invoked via compile_to_mlir the Halide IR will contain nodes that are only supposed to run on the host and not in an accelerator (such as a Call to _halide_buffer_get_host), which are not implemented.

Therefore my question is, should we consider the MLIR code as an "accelerator" that can only run loops, or also code that can also run on a host?

I would like to see a quick readme with minimal info on how you set up/installed MLIR and possibly a shell script that generates something through this path and compiles it with mlir-opt or similar.

In my system (Fedora) I just installed llvm-devel and mlir-devel and CMake was able to detect them without problems.
When compiling LLVM manually, make sure to add mlir to the LLVM's CMake option LLVM_ENABLE_PROJECTS.

@steven-johnson
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Hey, just wanted to check in and see where this PR stands. Is it waiting on feedback?

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xerpi commented Aug 4, 2023

Hey, just wanted to check in and see where this PR stands. Is it waiting on feedback?

Indeed. I have open questions about how to better integrate the MLIR Codegen. See my previous message for the details.

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Hey, just wanted to check in and see where this PR stands. Is it waiting on feedback?

Indeed. I have open questions about how to better integrate the MLIR Codegen. See my previous message for the details.

Ah, gotcha -- unfortunately @zvookin has been away on leave for a couple of months and it looks like no one took over the responsibility here. I'll bring this up and see who can take it over.

@shoaibkamil shoaibkamil self-requested a review August 4, 2023 21:01
Also adds compile_to_mlir methods to Func and Pipeline.
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xerpi commented Oct 28, 2023

No code changes, just a rebase.

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3 participants