GitHub - gupta-utkarsh/alu-8bit: Verilog Code for an 8-bit ALU

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
_xmsgs		_xmsgs
iseconfig		iseconfig
adder_8_bit.v		adder_8_bit.v
adder_8_bit_test.v		adder_8_bit_test.v
adder_8_bit_with_overflow_test.v		adder_8_bit_with_overflow_test.v
adder_with_overflow.v		adder_with_overflow.v
alu.v		alu.v
alu_8_bit.xise		alu_8_bit.xise
alu_test.v		alu_test.v
alu_with_register_file.v		alu_with_register_file.v
alu_with_register_file_tb.v		alu_with_register_file_tb.v
and_8_bit.v		and_8_bit.v
and_8_bit_test.v		and_8_bit_test.v
four_to_one_mux.v		four_to_one_mux.v
four_to_one_mux_test.v		four_to_one_mux_test.v
fulladder_1_bit.v		fulladder_1_bit.v
fulladder_1_bit_test.v		fulladder_1_bit_test.v
multi_8_bit.v		multi_8_bit.v
multi_8_bit_test.v		multi_8_bit_test.v
overflow_detection.v		overflow_detection.v
overflow_detection_test.v		overflow_detection_test.v
reg_file.v		reg_file.v
reg_file_test.v		reg_file_test.v
xor_8_bit.v		xor_8_bit.v
xor_8_bit_test.v		xor_8_bit_test.v