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The IR generated from the DSLX code that uses send operations in match statements seems to be incorrect. In the code attached below, the DSLX test shows that send operation happens only in the "A" state (only in one branch of the match statement), while the generated IR description performs the send in each iteration of the next() regardless of the state of the proc.
I suspect that the send command in the IR model should have a predicate that would cause the send to be executed only in the "A" state.
DSLX code:
enum Status: u1 {
A = 0,
B = 1
}
proc DummyProc {
channel_s: chan<Status> out;
init {
zero!<Status>()
}
config(
channel_s: chan<Status> out
) {
(channel_s,)
}
next(tok: token, state: Status) {
let state = match (state) {
Status::A => {
Status::B
},
Status::B => {
let tok = send(tok, channel_s, state);
Status::A
},
_ => fail!("impossible_case", zero!<Status>())
};
state
}
}
It is also visible in the generated verilog and vcd file. I upload the code here: antmicro@9d0f7cf. Below I attached the diagram generated from vcd file, which shows that the Verilog generated from the DSLX behaves differently than the original proc.
Another problem is that the test with enabled comparision between the DSLX and IR/JIT does not return any errors.
It will generate a file bazel-bin/xls/examples/send_match_verilog.ir, which I provided above.
The test that compares IR model and DSLX and passes (but shouldn't) can be run by bazel test //xls/examples:send_match_dslx_test.
Expected behavior
The expected behavior is that the send command in IR has a proper predicate. If it is illegal to put a send command inside a match statement, the error should be thrown instead.
Screenshots
Environment (this can be helpful for troubleshooting):
OS: Debian
Version: 12
The text was updated successfully, but these errors were encountered:
Describe the bug
The IR generated from the DSLX code that uses
send
operations inmatch
statements seems to be incorrect. In the code attached below, the DSLX test shows thatsend
operation happens only in the "A" state (only in one branch of thematch
statement), while the generated IR description performs thesend
in each iteration of thenext()
regardless of the state of the proc.I suspect that the
send
command in the IR model should have a predicate that would cause thesend
to be executed only in the "A" state.DSLX code:
IR code:
It is also visible in the generated verilog and vcd file. I upload the code here: antmicro@9d0f7cf. Below I attached the diagram generated from vcd file, which shows that the Verilog generated from the DSLX behaves differently than the original proc.
Another problem is that the test with enabled comparision between the DSLX and IR/JIT does not return any errors.
To Reproduce
Steps to reproduce the behavior:
bazel build //xls/examples:send_match_verilog
bazel-bin/xls/examples/send_match_verilog.ir
, which I provided above.The test that compares IR model and DSLX and passes (but shouldn't) can be run by
bazel test //xls/examples:send_match_dslx_test
.Expected behavior
The expected behavior is that the send command in IR has a proper predicate. If it is illegal to put a send command inside a match statement, the error should be thrown instead.
Screenshots
Environment (this can be helpful for troubleshooting):
The text was updated successfully, but these errors were encountered: