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Adding some RTI docs and comments. Also tracing that some be removed.…
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Original file line number | Diff line number | Diff line change |
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RTI | ||
### | ||
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RTI Blocks | ||
========== | ||
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entity / architecture / package / process / block | ||
------------------------------------------------- | ||
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* `Next_Context := (Base => Context.Base+Self.Loc, Block => Self)` | ||
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* Loops over all the children in the block. | ||
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* All the children receive the same context. | ||
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generate_body | ||
------------- | ||
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* `Next_Context := Context` | ||
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* A generate body is transparent. It contains all the children there, | ||
but the context still points to the top generate statement. | ||
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* All the children receive the same context. | ||
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if_generate / case_generate | ||
--------------------------- | ||
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* At the location Context.Base + Self.Loc there is | ||
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* instance_pointer field | ||
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* block_id field | ||
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* `Next_Context = (Base => instance_pointer, Block => Self.Children(block_id))` | ||
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* I think this is how it works: | ||
During elaboration we work out which of the children | ||
is selected and create the structure with the | ||
instance pointer pointing to where that childs | ||
info is getting placed, and the block_id indicating | ||
which of the children was selected. | ||
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for_generate | ||
------------ | ||
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* At the location Context.Base + Self.Loc there is | ||
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* for_instance_pointer field | ||
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* `Next_Context := (Base => for_instance_pointer + i*size, Block => Self.Child)` | ||
where i is the loop index, and size is Self.Size | ||
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* A for_generate contains a generate_body as it's only child. | ||
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* The first element in that generate_body is an iterator. | ||
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* That iterator has a type, and we assume that the type of that | ||
iterator is specified within the same context as the for_generate. | ||
This is typically true because, in practice, we always define the | ||
iterator type implicitly in the for_generate statement. Ghdl | ||
create an anonymous type definition immediately preceding the | ||
for_generate. | ||
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instance | ||
-------- | ||
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Example | ||
======= | ||
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.. code-block:: Vhdl | ||
library ieee; | ||
use ieee.std_logic_1164.all; | ||
entity myxor is | ||
port ( | ||
a: in std_logic_vector(2 downto 0); | ||
b: in std_logic_vector(2 downto 0); | ||
c: out std_logic_vector(2 downto 0) | ||
); | ||
end entity; | ||
architecture arch of myxor is | ||
begin | ||
gloop: for i in 0 to 2 generate | ||
c(i) <= a(i) xor b(i); | ||
end generate; | ||
end architecture; |
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