Simple RISC Computer (ezRISC)

George Trieu, Matt Garvin

Datapath Architecture

The datapath architecture is based off of a 1-BUS design.

Components

PC: Program Counter
- 32-bit Register
- Stores the memory address of the current instruction
IR: Instruction Register
- 32-bit Register
- Stores the instruction fetched from memory
General Purpose Register File
- Collection of 16 32-bit Registers Numbered from R0 to R15
MAR: Memory Address Register
- Stores the address that will be queried from memory
MD_MUX/MDR: Memory Data Multiplexer/Memory Data Register
- MD_MUX
  - 32-bit 2-1 Multiplexer
  - If Reading from memory, pass memory data to MDR
  - If Writing to memory, pass bus data to MDR
- MDR
  - 32-bit Register
  - Stores data to be written to (Read = 0) or read from (Read = 1) memory
HI: High Register
- 32-bit Register
- Stores the upper 32 bits of the 64-bit Z Register
  - Remainder in Division Operations
LO: Low Register
- 32-bit Register
- Stores the lower 32 bits of the 64-bit Z Register
  - Quotient in Division Operations
Y_MUX/Y: Y Multiplexer/Y Register
- Y_MUX
  - 32-bit 2-1 Multiplexer
  - If used to increment PC, select constant 0x1
- Y Register
  - 32-bit Register
  - Stores one of the operands used in ALU calculations
ALU: Arithmetic Logic Unit
- Performs arithmetic and logic operations
Z: Z Register
- 64-bit Register
- Stores the result of the arithmetic operation
- Can output upper or lower 32-bits onto the bus

ALU Architecture

The ALU is made up of different modular operations, that is selected using a 16-1 MUX.

Select and Encode Logic

Special Note: When the purple logic expression on the left is true:
- jal OP Code is 10100
- This means this is a 'jal' (jump and link) instruction
- It also means in this cycle, the current PC is pushed into the link register (R15)
- Forces the decoder to activate the link register (R15) lines.

Name		Name	Last commit message	Last commit date
Latest commit History 106 Commits
documentation		documentation
output_files		output_files
.gitignore		.gitignore
RAM.qip		RAM.qip
RAM.v		RAM.v
README.md		README.md
Seven_Seg_Display_Out.v		Seven_Seg_Display_Out.v
add_datapath_tb.v		add_datapath_tb.v
addi_datapath_tb.v		addi_datapath_tb.v
alu.v		alu.v
alu_tb.v		alu_tb.v
and_datapath_tb.v		and_datapath_tb.v
andi_datapath_tb.v		andi_datapath_tb.v
booth_32x32_mult.v		booth_32x32_mult.v
brxx_datapath_tb.v		brxx_datapath_tb.v
con_ff.v		con_ff.v
control_unit.v		control_unit.v
datapath.v		datapath.v
datapath_phase3.v		datapath_phase3.v
datapath_phase3_tb.v		datapath_phase3_tb.v
dec_2to4.v		dec_2to4.v
dec_4to16.v		dec_4to16.v
demo_ram_init.mif		demo_ram_init.mif
div_datapath_tb.v		div_datapath_tb.v
divider_non_restoring.v		divider_non_restoring.v
enc_32to5.v		enc_32to5.v
ezRISC.qpf		ezRISC.qpf
ezRISC.qsf		ezRISC.qsf
ezRISC.tis_db_list.ddb		ezRISC.tis_db_list.ddb
ezRISC_assignment_defaults.qdf		ezRISC_assignment_defaults.qdf
gp_register.v		gp_register.v
in_datapath_tb.v		in_datapath_tb.v
jal_datapath_tb.v		jal_datapath_tb.v
jr_datapath_tb.v		jr_datapath_tb.v
ld_datapath_tb.v		ld_datapath_tb.v
ldi_datapath_tb.v		ldi_datapath_tb.v
mdr.v		mdr.v
mfhi_datapath_tb.v		mfhi_datapath_tb.v
mflo_datapath_tb.v		mflo_datapath_tb.v
mul_datapath_tb.v		mul_datapath_tb.v
mux_32bit_2to1.v		mux_32bit_2to1.v
mux_32bit_32to1.v		mux_32bit_32to1.v
neg_datapath_tb.v		neg_datapath_tb.v
not_datapath_tb.v		not_datapath_tb.v
or_datapath_tb.v		or_datapath_tb.v
ori_datapath_tb.v		ori_datapath_tb.v
out_datapath_tb.v		out_datapath_tb.v
rol_datapath_tb.v		rol_datapath_tb.v
ror_datapath_tb.v		ror_datapath_tb.v
select_encode.v		select_encode.v
shl_datapath_tb.v		shl_datapath_tb.v
shr_datapath_tb.v		shr_datapath_tb.v
st_datapath_tb.v		st_datapath_tb.v
sub_datapath_tb.v		sub_datapath_tb.v

geotrieu/ezRISC

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Simple RISC Computer (ezRISC)

George Trieu, Matt Garvin

Datapath Architecture

Components

ALU Architecture

Select and Encode Logic

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