1.5 * curcap -> curcap + curcap / 2 in fs_path.cc
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This change has two ihmo positive implications: - The implicit conversion from double to int is avoided (Avoiding a warning). - No double is used at all, which could be significant in some scenarios.
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Committed upstream as a3fee5e |
stephanosio
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May 5, 2024
This commit includes the ARC patches from the zephyr-gcc12 branch of the foss-for-synopsys-dwc-arc-processors/gcc repository, the commits from 95370809fff1cf77839f5f6440d0602bcdc4b542 to e65f77588ccb6b5b3f9f84345772ec419d99d169: [ARCx] Configurations [ARCx] Populate constraints and predicates. [ARCx] Add subroutine calls [ARCx] Add placeholder in the md file Added constraints for short immediate variations. [ARCx] Update calls and sibcalls Changed name of constraints. update compare Push for compilation Added macros for constraints verification. Fixes Got the cc1! Cleanup gcc-mirror#1 [ARCx] Add frame info and prologue expand [ARCx] Add FUNCTION_VALUE hook First commit with arith define_insns. Forgot to change type list. [ARCx] Fix addsi3 in arith.md Add expand epilogue functions [ARCx] arc64_mov insns have been added [ARCx] Keep the fixes on generated MD's separated [ARCx] Usefull hacks [ARCx] Make it compliable again Added logic instruction rules (most of them). Removed include arith.md from arc64.md. Left logic.md. [ARCx] Introduce push/pop to arc64.md and more [ARCx] Add a hand-crafted arith.md [ARCx] Add target hooks for printing operands [ARCx] Use ldb/ldh and stb/sdh for movqi/hi [ARCx] Add the missing arith.md (hand-crafted one) [ARCx] Add movdi (the 64 bit move) [ARCx] More on calling convention [ARCx] Fix SP popping issue and use movl for movdi [ARCx] Treat SP register as a general register [ARCx] Add airthmatic instructins for DImode [ARCx] Reove unused passes [ARCx] Update print_operand and print_operand_address [ARCx] LIBGCC attempt adding configuration [ARCx] Fix emitting labels and aligns [ARCx] movqi: Add w6 immediate store [ARCx] Add the first ARC64 test (movqi) [ARCx] Update compare, signext and hooks (newlib) [ARCx] Fix type in .md for signext [ARCx] Extend test01 of movq [ARCx] add more test cases for movq Fixes [ARCx] break movq test [ARCx] enable movq-6 fix 2 [ARCx] mark movq-2 as fixed [ARCx] Add support to movq: immediate to memory Update sign/zero extend patterns, fail for FP ops [ARCx] Fix typo in movq-9 [MOV] Update movqi and movhi patterns. [LENGTH] Compute the length for st/ld type of instructions. [ARCx] update in movq tests. [LENGTH] Remove dead code and negate bool correctly. [ARCx] Add and, xor, ior, smin, smax, not, abs expands (and insns) [FIX] small fix in the template for LOGIC2 ops [FIX] Floats are passed in mem, fix rotatert. [ARCx] Improve on movq. [TST] Fix movq-2.c [FLOAT] Add a soft float move sf. [MD] Add movhi along with tests. [TST] Fix movh-6 test [TST] Add FIXMEs to the tests Comment out unimplemented expands [DBG] Emmit a mov sp,fp regardless of the offset [MD] Add movdi along with the tests Added libnosys to GCC specs. Fixed constraints to arc64_movqi. Fixed most of the issues with undefined references. [SYMBOLS] Split a 64bit symbol/const_int into hi/lo_sum. Don't return more than one reg Commented rule to fix zero_extend issues in dejagnu. Only return simple scalar datatypes Add trampolines Add iscompact attribute to jump Added all the soft insns to libgcc needed for DejaGNU tests. Fix computing frame size Fix restoring regs Fix restore regs Changed back to 8 the units per word for libgcc. Add muldi3 function Add div/mod 64bit routines Handle 64bit constants on ARITH ops Add arc64_nonmem_operand predicate More on handling 64bit constants Change stack boundary to 64 [MD] Swap dst and src for sign extend Add Sibcall hook fix splitting 64 bit constants Handle 64bit constants for CMP instructions Add 32bit variant for clz, ctz, ffs, parity and popcount Handle SP updates with large 64bit constants. Fix anon args Fix tests Improve trampoline [CTOR/DTOR] link with crti,crtend,crtbegin, and crtn [STACK] Align everything Update alignments, trampoline, and add dump stack info Fix trampoline. Cleanup attr-alloc_size-11.c XPASS Add partial bytes hook Fix typo [PIC] Add pic support for variables [PIC] Emit @plt for calls [PIC] Add small/large PIC memory model. [PIC] Disable -fPIC impl as it is not yet supported by tools. [TLS] Add basic TLS support. [ARC] LIBGCC: Allow configure for olde good 32-bit ARC (gcc-mirror#83) [SPEC] Add LINK_SPEC to elf Fixed issue related to offset size of conditional branch instructions. First builtins added to arc64 (nop, lr, sr, flag, brk). TI mode ADD and SUB pattern using respective carry instructions. arc64: Fix choosing short insn arc64: Add shifted adds and subs ops arc64: fix bcc_s instructions arc64: Add DIV/REM 32/64 instructions arc64: add mpy(l) instructions arc: add dbnz pattern arc64: add short version instruction. add new insns typo fix arc64: fix printing Low nibble needs to be unsigned. arc64: Add rotate variants arc64: Generate reg index and scalled accesses arc64: experimental 2 regs/address arc64:non functional insn_cost arc64: CMP0: and,ior,xor, sex, ext arc64: add scalled s9 support arc64: scalled shimm for add/minus arc64: Add conditional execution arc64: CSTORE force to register large constants. arc64: Add short mov,ld, and st instructions arc64: Remove F16_OP_IMM instructions arc64: fix builtins pattern, types and expand routines arc64: Add C/C++ preprocessor defines arc64: Fix cmpsi' s3 short insn constraint. arc64: Honor memory model large for calls. arc64: set sibcall returns size to 4 arc64: Remove unecesary attributes arc64: Emmit @u32 arc64: UNSPEC addresses are using limm arc64: Fix typo in call ce instructions arc64: Add basic DWARF macros arc64: Add exception handling support. arc64:fix setcc instructions when dealing with 64bit imm arc64:fix crtstuff to use proper 64bit pointers arc64: Add dummy mcpu option arc64: fix: Memory operands are using implicit brackets arc64: Add linux configuration arc64: Update to gcc 10 release arc64: Add MI_THUNK output. arc64: baremetal doesn't use dwarf unwinding arc64: Use pc-rel addressing also for non-pic medium symbols arc64: Rename ARC64_UNSPEC_GOTOFF to ARC64_UNSPEC_PCREL arc64: Update combiner patterns arc64: Add reload variant for dbnz instruction arc64: Add R30 as epilogue used when TLS arc64: Tell to the compiler we want DWARF2 arc64:Implement EH_USES when TP is used. arc64: fix tls detection in assembler ar64: hack: The file I/O doesn't fully work for nsim64 arc64: Add btst, sub.f and rsub.f. Improve ifcvt. Implementation of atomics for ARC64. arc64: Add doloop_end pattern. Implemented builtin for trap_s. arc64: Deal with out of bounds target for dbnz insn. Fix issue with atomics on glibc toolchain build. arc64: Accept SYM+OFFSET constants WIP for Review: Make atomic option enum arc64: Fix target tests. arc64: Atomic builtin only defined if we have atomic ops arc64: Check for atomic ops ARC64: atomics: enable baseline llock/scond (gcc-mirror#92) arc64: Code cleanup arc64: simple cleanup arc64: fix warning arc64: Accept only PCREL unspecs for mov instruction. arc64: Add table-jump support. arc64: Handle TLS unspecs more strictly arc64: Swap saving order for BLINK and FP arc64: Refurbish address gen for SMALL/MEDIUM mem types. arc64: fix 64bit address gen ARC64: builtin: generate a define for cmodel arc64: Cleanup atomic1 implementation arc64: Move static functions to beging of the file (txt cleanup) arc64: Add the new ARCv3 ATO instruction support. arc64: add unaligned access, improve addN patterns. arc64: Enable unaligned by default, add C-macro arc64: HACK: volatile pointers will use .di arc64: Remove mmpy64 option arc64: add missing hook. Improves code gen for 32 bit arc64: Remove compare with zero for mpyl insns arc64: Add bitscan instructions. arc64: Update predicate commutative ops, add zero-ext predicate ops. arc64: Use a larger value for MOVE_RATIO arc64: Add SRL/LRL builtins arc64: Address scaling cannot be used with pre/post address modifiers arc64: DIV/REM force to reg 64b immediates arc64: Enable div/rem instructions by default ARC64 Revert back to aligned data accesses only for now (gcc-mirror#94) arc64: Add SP floating point instructions. arc64: FP use stock legit addr. Introduce compiler macro. arc64: Re-enable jump table arc64: Add fnmadd fnmsub based patterns used when honoring zeros arc64: Add movcc and predicated fmov arc64: Disable movcc insns arc64: Another add<M> rA,rB,RC << M variant. Usefull for addr arc64: casesi: emit unlikely jump arc64: Add --with-fpu config option arc64: Turn on bitscan instructions. arc64: cleanup unused vars arc64: Add mov.f instruction arc64: Fix casesi snafu arc64: Refactor ABI, fix fpABI snafu arc64: Add IEEE half-precision support. arc64: don't use soft-fp routines for hf conversion arc64: Add support for half precision and integer vectors arc64: Add pack, mpy and vec extract instructions arc64: Fix FP vector patterns & add FMA ones arc64: Add vec_duplicate arc64: Fix warning arc64: Update softfp moves, fix warnings arc64: forgot this one revert atomic mod arc64: Add vector reduction pattern for 2xV arc64: Add Vectorizer cost hook. arc64: builtin-apply2 doesn't work with ARC64 FP ABI arc64: Add 64b SIMD fp support, and double precision fp hw support arc64: Fix matching scalled address. arc64: Add extra specs. arc64: Add msimd option which enables intSIMD instructions. arc64: disable incompatible test. arc64: f0-f7 are used to pass args in hard-floats ABI arc64: Add 128SIMD support. arc64: Add vect reduc pattern for v2si, use vadd2h/vsub2h for 16b ops. arc64: Add zero_extend patterns arc64: Provide a mapping from gcc regs to dwarf regs arc64: typo fix MAINLINE: Change test to check our vec_perm arc64: Add (integer) vector perm const arc64: Add int SIMD vec_shl, fix fp SIMD vec_extract arc64: Add m128 support for function's prologue/epilogue [multilib] Add a library for -m128 arc64: Initial cost control for loads/stores and most used patterns arc64: Fix immediate for mpy(u)w instructions. arc64: Fix mpy(u)w instruction arc64: Update split address for PRE_MOD addresses arc64: Using m128 in combination with mfpu defaults to mfpu libs arc64: Allow store instructions to store an imm. arc64: Update stl length to 8. arc64: Allow signed 32bit immediates for 64bit arith insns arc64: Use a long jump when crossing arc64: Add MAC/MACD/VMAC2H signed/unsigned instructions arc64: Increase div costs, encourage syntetic ones. arc64: type fix naming arc64: Update costs multiplication, addresses, and sgnext arc64: Add compare with 0 xbfu insns arc64: Fix xbfu.f operands arc64: Add patterns matching dmacwh[u], dmpywh[u] and dmach arc64: Improve matching .f instructions arc64: Add BBIT[0/1][L] pattern arc64: fix bbit range arc64: Add BRcc combiner patterns arc64: Use sign_extend when loading. arc64: fp: reused the ARCv2 C macros for code-diversity management (gcc-mirror#97) arc64: Add support for 34bit PLT calls m64/m128: Add cpymem expand arc64: Add delay slot scheduler arc64: Fix movmisalign patterns, and scale ld/st imms Remove unused files arc64: Remove 'Report'. arc64: Update madd instructions to avoid dead code removal. arc64: force to reg in vec_perm. arc64: Add dot to matomic option description. arc64: Update tests. arc64: memcpy: update move ratio values. arc64: Deal with 128b constants. arc64: Change maximum number of bytes to allow 128 moves. arc64: Remove duplicate macro arc64: Mark blink alive when emitting a call to __tls_get_addr arc64: Add PROFILE_HOOK arc64: add macro to signal Hard-float ABI (gcc-mirror#98) arc64: FP ABI update call used regs up to f15 arc64: Split 128b PIC addresses. arc64: Add convertions from HF to DF and back arc64: Fix mac constraints snafu. arc64: Use swap with v2hi vectors. arc64: Enable unaligned access for elf targets arc64: Add MPYD(U), change MULT costs. arc64: Fix dmpy int constraints arc64: Add dmpywh instruction (used scalar) arc64: Update accsi to accrn constraint arc64: Improve and fix potential issues with 16b scalar ops arc64: Update zero_ext cost, add new peephole pat arc64: Update zero extend from hi. arc64: Add sched info arc64: Fix addressing local symb (large) arc64: Use dedicated constraint for store type mems. arc64: Fix softfp move constraint letter snafu arc64: Fix snafu when computing ld/st insns sizes. arc64: Enable removable redundant extension instructions. arc64/arcv2: fix triplet snafu arc64: Add documentation. arc64: Update constraints arc64: Enforce the ld limm to be within 32bit range. arc64: Widen the scope for base/index regs arc64/arcv3: Check BE for TLS. arc64: Don't use implicit dmacwh(u) output. arc64: Add new mpyd/mac and mac/mac sched rules arc64: Disable speculation when filling delay slots arc64: TLS add a move before calling tls_get_addr arc64: Use a conservative size estimation for branches when computing loop body size. arc64: Introduce core register set arc64: Introduce a fallback path when dbnz target is too far [arc64] Add Exception handling builtins [arc64/libgcc] Unwinding out of signal handler arc64: Update dbnz's predicate and constraints arc64: Update store c-letters for vector ops arc64: Update FMA(s) instructions. Add Vector FP neg emulation arc64: Fix dmpywh<u> instructions with immediate operands. arc64: remove faulty add/sub 16b pattern arc64: Precompute TLS arc64: Consolidate pushl/popl instructions arc64: Add bswap32/64 ops arc64: Keep close MAC-MOV instructions arc64: Enable slow byte access for more efficient bitfield code. arc64: Use 'int' as base for wchar_t arc64: Add trap instruction arc64: Emit aq.rl flags for new AMOs. arc64: Use a PLUS operation while spliting the 64b imms as it generates more efficient code arc64: Update rtx_costs factoring in mode size arc64: Update add/sub with carry instructions arc64: Add {add, sub, neg, mult} overflow patterns arcXX: Fix overflow for mpy's arc64: Add SETcc.f instruction. arc64: Update alignments, add malloc alignment Revert "arc64: Update alignments, add malloc alignment" [arc32] Initial commit [arc32] iterate the call_insn [arc32] iterate the sibcall_insn [arc32] parameterise stack and parm boundaries [arc32] pass "-mcpu=arc32" to gas arc32: Update call templates for 32 bit arc32: Disable 64bit instructions when 32bit arcxx: Enable BI/BIH instructions by default arc32: Changes to libgcc arc32: Add CRT_CALL_STATIC 32b variant arc32: Update MOVE_MAX and handling of const(...) printing arc32: Use ti emulation only for arc64 builds [arc32] Disable muldi3_highpart [arc32] Add m32 flag to multilib [arc32] Merge <optab> modes to cover DImode correctly [arc32] Enable PC relative moves arc32: Protect EPI iterator in 32b mode [arc32] Trampoline generation handles 32 and 64 bits arc32: Use "plt" iso "plt34" for addressing arc64: Generalize split of double moves arc32: Select the right emulation for 32b arc32: Fix printing float numbers arcv3: Use UNITS_PER_LIMM macro for FPU arc32/dg.exp: Fix stack-usage-1 arc32: Add "-mll64" option arc32: Disable "TARGET_LL64" when target isn't 32-bit arc32: Introduce 64b double move splits arc32: Update BIGGEST_ALIGNMENT. arc32: Fix split double move arcXX: Add mpyf test for flags update arcXX: Consider the element of COMPLEX for reference pass check arc32: Add -mcpu=hs{5,6}x option instead of -m{32,64} arc32: Add new ARCv3:32 triplet arcXX: Fix warning. arc64: Linux target is defaulting to 64bit arches arc64: Cleanup rotate patterns arc64: enable simple cc-reg mods arc32: skip compile.exp=20000804-1.c arc64: Don't use vadd2h as 16b scalar op arc64: Update sched handling of acc regs. Add extra peephole step. arc64: Add NAKED attribute arc64: Add INTERRUPT attribute arc64: Honor memory models for BL instructions. arc64: Change modifier %h to %H, and %H to %V arc64: Add BRcc support, peephole2 tier. arc64: Update BRcc implementation. arc64: Update rtx costs (16b) arc32: Update LARGE memory model for HS5x arc64: Update specific tests to work for HS5x arc32: Honor large memory model for calls arc64: Update predicated execution patterns. Disable BBITx gen. arc64: Don't use pc-rel access for local symbols. arc64: Update 64bit add/sub instructions, when 32b used, carry operations are generated. arc64: Fix mpy snafu arc64: Enable unaligned access for linux toolchain arc32: add lnx target triplet arc32: add thread_pointer builtin arc32: add tls offset arc32: temporary fix for PIC symbols arc32: fix libgcc config entry for hs5x arc32: Update msimd option for HS5x CPUs arc64: Don't allow const into mov operands arc64: Update legitimate CONSTANT hook. Update movsi pattern. arc64: Add zeroextend patterns for add[123],asl,asr, and lsr arc64: Force any symbol out of the constant pool. arc64: Don't allow symbols as constants when PIC arc32: Allow 64b moves only when we have LL64 arc32: Update ldd/std mod letters. arc32: Enable DBNZ for ARCv3/32 arcv3: update legitimate_address_1_p() to cover ldd arcv3: adapt {restore,save}_callee_*() for ldd/std arc64: Add zero-extend xbfu arc32: Add "ldd/std" support arc32: Fix address scaling for double loads/stores arcXX: Fix saving/restoring callee saved registers for double loads/stores arc32: Enable 64b integer SIMD moves arc64: Scalled offsets for double access addresses needs to be smaller than s9 field arc32: Enable dot_prod4hi pattern. arc64: Set schedule issue rate to 2 arc32:multilib: Update cpu list with hs68 and hs58 arc64: Update scaling tests arc64: Fix double move spliting snafu arc64: Update vect_perm cost. arc32: Update v4hi vector reduction pattern arc64: Make SIMD default for hs{5,6}8 ARC32: Fix vec wideining mult arc64: Add vec_init pattern for v2si and v4hi vectors arc64: Add predicated version for sign extend using ASR/ALR arc64: Add accelerated vector reduction expands arc64: Fix typo in {s,h,d}exch unspec names. arc64: Support permutation vectors using vfexch insn. arc64: Add support for VFUNPKL/VFUNPKM insns arc64: Add vshuf tests for Float16 arc64: Add support for FVPACKL/FVPACKM arc64: Add support for FVBFLYL/FVBFLYM arc64: Cleanup arc64_simd_unpk func. arc64: Add cadd90/cadd270 for FP vectors arc64: Add cadd90/cadd270 for v2hi and v2si vectors arc64: Fix predicate pattern for mulhisi arc64: Add vpack2h shuffle patterns arc32: Fix vec_pack_trunc snafu arc64: Add v2hi init pattern. Not yet enabled arc64: Add vmax2/vmin2 instructions. arc64: Update vmax/vmin patterns arc64: Update unspec patterns arc64: Add combiner pattern for vpack2hl arc64: Add more vpack4hl shuffle patterns arc64: Enable movcc and cbranchcc instructions arc64: Add negcc and notcc patterns arc64: fix negl snafu arc64: Update notcc negcc patterns arc64: Optimize cmov pattern arc64: Update conditional mov patterns for FP modes arc64: Add reloads for cnot/cneg arc64: Cleanup md iterators arc64: Add DWARF2 alternate CFA column. arc64: Fix DWARF2 alternate CFA column patch arc64: Add an extra option to disable the vpack2h instructions. arc64: Update mov.f pattern arc64: Add fp-vector reverse shuffle arc64: Add combiner pattern for vpack2wl arc32: Add vect shifts for v2si arcv3: Add the option to use FPRs for memory options arc32: Adjust offset only when offset is positive arc64: Add config support for --with-cpu=... arc64: Update printing name of regs in ASM prologue arc64: Update FP-ABI: all record types are passed via R-regs arc64: Improve printing info about function frame arc64: fix sanfu arc64: unsigned max/min ops are synthesized using movcc, compare operands can be two non-regs, fix it arc64: Update compare test arc64: Remove F16_ADD_IMM instructions arc64: Chance fld128/fst128 to fldd64/fstd64 arc64: Guard remaining VPACK instructions arc64: Update required by gcc12 arc64: Allow VPACK* insn with msimd opt arc64: Update sth w6 instruction matching constraint arc64: Add brgt,brhi,brle and brls instructions Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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This change has two ihmo positive implications:
The implicit conversion from double to int is avoided (Avoiding a warning).
No double is used at all, which could be significant in some scenarios.
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