Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Fixes typo in verilog model so it matches the schematics #21

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

Fixes typo in verilog model so it matches the schematics #21

wants to merge 2 commits into from

Conversation

jotego
Copy link
Contributor

@jotego jotego commented Aug 12, 2023

This typo fix will make the L1 signal match the schematic:

imagen

The inverted REG11[5] is used in the upper NAND gate

furrtek
furrtek approved these changes Nov 21, 2023
View reviewed changes
Copy link
Owner

@furrtek furrtek left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thank you !

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@furrtek furrtek furrtek approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.

None yet
2 participants
@jotego @furrtek