Releases: firesim/firesim
FireSim 1.18.0 Release
Added
- Mainline U200 Support (by @abejgonzalez in #1614)
- Expand TracerV to support more than 7 IPC with FMR fix (by @abejgonzalez in #1596)
- Add default reports for Alveo (by @abejgonzalez in #1664)
- Major re-organization of Vivado U2*0 *.tcl + Support for 4 DRAM channels on U250 (by @abejgonzalez in #1669)
Changed
- Bump to chisel3.6 (by @jerryz123 in #1594)
- Bump the garnet-submodule to be compatible with Vivado 2023.1 (by @william-lyh in #1620)
- TracerV binary mode - Print cycle + insts only (no padding) (by @abejgonzalez in #1643)
- Remove Dromajo in favor of Spike cosimulation (by @abejgonzalez in #1644)
- Update BlockDevBridge to not use Parameters (by @jerryz123 in #1651)
- Move BRAMQueue to
targetutils
(by @abejgonzalez in #1673) - Remove BRAMQueue | Add working FireSimQueueHelper (by @abejgonzalez in #1679)
Fixed
- Bump conda-reqs | Use existing conda for conda-lock (by @abejgonzalez in #1601)
- Fix publish scala docs (by @abejgonzalez in #1631)
- add missing step for flashing local FPGAs (by @joey0320 in #1632)
- Don't translate to json in workflow monitor to prevent error (by @abejgonzalez in #1640)
- fix kill pass terminate condition (by @joey0320 in #1549)
- Bump Chipyard (by @abejgonzalez in #1645)
- Update Configuring-Required-Infrastructure-in-Your-AWS-Account.rst (by @abejgonzalez in #1647)
- Remove OS_VERSION in machine-launch-script.sh (by @sagark in #1662)
- Detect v/sv files to regen. jars (by @abejgonzalez in #1665)
- Update entry.cc to always have loadmem.h available (by @abejgonzalez in #1687)
Uncategorized
- Fix doc substitution (copy #1621) (by @mergify[bot] in #1624)
- Revert changes to awstools.py (by @abejgonzalez in #1626)
- Update local bitstream(s) for PR #1627 (
whitespace-rebuild-fis
) (by @github-actions[bot] in #1628) - Update AGFI(s) for PR #1627 (
whitespace-rebuild-fis
) (by @github-actions[bot] in #1629) - Update local bitstream(s) for PR #1620 (
garnet-2023-bump
) (by @github-actions[bot] in #1637) - Update local bitstream(s) for PR #1596 (
revamp-wide-tracerv-w-fix
) (by @github-actions[bot] in #1638) - Update AGFI(s) for PR #1596 (
revamp-wide-tracerv-w-fix
) (by @github-actions[bot] in #1639) - Update Cospike.rst (by @raghav-g13 in #1648)
- Update local bitstream(s) for PR #1651 (
bdbridge
) (by @github-actions[bot] in #1652) - Update local bitstream(s) for PR #1651 (
bdbridge
) (by @github-actions[bot] in #1654) - Update AGFI(s) for PR #1651 (
bdbridge
) (by @github-actions[bot] in #1655) - Update AGFI(s) for PR #1651 (
bdbridge
) (by @github-actions[bot] in #1659) - Update local bitstream(s) for PR #1651 (
bdbridge
) (by @github-actions[bot] in #1658) - Update AGFI(s) for PR #1651 (
bdbridge
) (by @github-actions[bot] in #1661) - Update local bitstream(s) for PR #1651 (
bdbridge
) (by @github-actions[bot] in #1660) - Update local bitstream(s) for PR #1672 (
sep-ci
) (by @github-actions[bot] in #1674) - Update testchipip imports to match new testchipip packaging (by @jerryz123 in #1681)
- Remove extraneous -include flags to verilator (by @jerryz123 in #1682)
- Update rocket-chip-blocks naming (by @jerryz123 in #1685)
FireSim 1.17.1 Release
Added
- Bucket log docs (by @joey0320 in #1575)
- Add release note automation (by @abejgonzalez in #1595)
Changed
- Use bar-tender specific access (by @abejgonzalez in #1558)
- CI modifications - Support Vivado 2022.1, New CI machine(s) (by @abejgonzalez in #1592)
Fixed
Full Changelog: 1.17.0...1.17.1
FireSim 1.17.0 Release
Support for several new local FPGA boards added: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims.
Added
- Manager support for custom TARGET_PROJECT by @sagark in #1495
- Bare Xilinx U250/U280 shell support by @bgottschall @davidmetz @abejgonzalez in #1497
- Buildbitstream CI by @abejgonzalez in #1458
- FireSim Support for Xilinx VCU118 by @sagark in #1507
- add mcs command to implementation script for u250 by @kevindna in #1518
- Xcelium + Verilog-as-Top by @abejgonzalez in #1527
- Add U250/VCU118 bitstream builds to CI by @abejgonzalez in #1522
- Support building U280 in CI by @abejgonzalez in #1544
- FireSim Support for RHSResearch Nitefury II + various fixes by @sagark in #1525
Changed
- Update Makefile to be non-parallel by @abejgonzalez in #1488
- Dedup CI uartlog checking | Add more checks by @abejgonzalez in #1489
- Bump to chisel3.5.6/latest rocketchip by @jerryz123 in #1476
- Clear screen before prompt by @abejgonzalez in #1491
- Update sample_config_hwdb.yaml for Gemmini build by @abejgonzalez in #1490
- Create separate security group for build/run farm instances that is only accessible from within the firesim VPC by @sagark in #1492
- Bump Verilator to 5.006 by @abejgonzalez in #1471
- Rename SerialBridge to TSIBridge by @jerryz123 in #1500
- bump aws-fpga for fix when using exactly 3 of 4 mem channels by @sagark in #1505
- EC2 AMI update by @joey0320 in #1517
- Split buildbitstream tag into two tags by @abejgonzalez in #1528
- Update CI workflow to use login shell | Misc. cleanup by @abejgonzalez in #1532
- Update xclbin(s) for PR #1530 (
bumprc-bitstream
) by @github-actions in #1533 - Bump to latest rocketchip by @jerryz123 in #1526
- Use fat jar to reduce SBT invocations instead of cached classpath by @abejgonzalez in #1529
- Update AGFI(s) for PR #1536 (
revert-tv-wide
) by @github-actions in #1538 - Touch *.jar assembly files by @abejgonzalez in #1540
- conda-lock=1.4, Loosen/restrict conda req. specs by @abejgonzalez in #1539
- Update AGFI(s) for PR #1525 (
nitefury_ii
) by @github-actions in #1545 - Update AGFI(s) for PR #1543 (
rename-scripts
) by @github-actions in #1546 - Rename sourceme-f1-manager.sh to sourceme-manager.sh by @sagark in #1543
- Update local bitstream(s) for PR #1525 (
nitefury_ii
) by @github-actions in #1548 - fix fased useHardwareDefaults setting bug by @PKUZHOU in #1499
- Revert "Expand TracerV to support more than 7 IPC (#1383)" by @abejgonzalez in #1536
- Misc. CI Cleanup - Local Cleanup Parallelism + Clobbered Buildbitstream PRs by @abejgonzalez in #1551
- Update AGFI(s) for PR #1525 (
nitefury_ii
) by @github-actions in #1553 - Update local bitstream(s) for PR #1525 (
nitefury_ii
) by @github-actions in #1554
Fixed
- Fix conda lockfile docs / make lockfile generation easier by @t14916 in #1478
- Dedup CI uartlog checking | Add more checks by @abejgonzalez in #1489
- Fix open files only on sudo by @abejgonzalez in #1493
- update assert in timingmodel to allow BURST_FIXED w/len=0 by @sagark in #1496
- Fix first-time-user setup docs by @sagark in #1498
- Fix Scala test on machines with multiple simulators by @abejgonzalez in #1474
- fix main.o build dependency on generated const.h by @sagark in #1504
- Fix
buildbitstream
CI issues + Addxclbin
bitstream generation by @abejgonzalez in #1508 - Misc. U250/U280 FPGA Fixes by @abejgonzalez in #1502
- Various Fixes by @abejgonzalez in #1521
- Misc. Fixes (Downgrade cryptography package, pin packages, fix non-firesim make project compilation) by @abejgonzalez in #1534
- Bump CY by @abejgonzalez in #1555
- automatically try newer hotfix versions of AMI in manager by @sagark in #1559
- Local FPGA managerinit QoL Fixes by @sagark in #1561
- changed mmap to xdma_user instead of pci resource by @cyyself in #1564
FireSim 1.16.0 Release
Vitis documentation updates, re-work of FireSim driver code, URI support for tarball/xclbins, Various bumps
Added
- Vitis: support different bitstream build strategies by @davidbiancolin in #1270
- vitis: Support frequency settings provided at bitstream build by @davidbiancolin in #1281
- Adding support for Azure CI by @t14916 in #1262
- Add apply method that takes ReferenceTarget parameter in RAMStyleHint by @russell-horvath in #1306
- adding a Plusargs Bridge, with unit tests and TutorialSuite tests by @sifive-benjamin-morse in #1291
- Add CI typechecking by @abejgonzalez in #1325
- Added UART bridge test by @nandor in #1326
- Added SimpleRocketF1Tests by @nandor in #1330
- Add an Assert-mode for TerminationBridge; expand testing by @davidbiancolin in #1324
- Introduced an interface to capture the user-defined logic of a simuation by @nandor in #1328
- Added a test for the BlockDevBridge by @nandor in #1335
- Added a root widget class and a low-overhead RTTI mechanism by @nandor in #1382
- Added a bridge registry to own all bridge instances by @nandor in #1369
- Added a test for memory accesses and LoadMemWidget by @nandor in #1433
- Add scalaFix by @sifive-benjamin-morse in #1393
- Add VCS metasimulation to CI by @abejgonzalez in #1396
- Add CI for Vitis driver outside of FPGA sims by @abejgonzalez in #1414
- Add reports and checkpoints section to vitis readme by @russell-horvath in #1412
- Add option to the F1 driver to load an AGFI by @nandor in #1434
- Add URI support to tarball path and xclbin path by @sifive-benjamin-morse in #1432
- Add ci:persist-prior-workflows tag to allow prior workflow to run until completion by @sifive-benjamin-morse in #1449
- Add uartlog checking to Linux boots in CI by @abejgonzalez in #1454
- Add
build_farm_tag
field to AWS EC2 build farm recipe by @abejgonzalez in #1457 - Add
buildfarmprefix
to AWS resource dict by @abejgonzalez in #1462 - Add PyTest docs by @abejgonzalez in #1269
- Put instPath before label in AutoCounter output by @timsnyder-siv in #1274
- Add workshop info to README.md by @sagark in #1411
- Bump to latest rocket-chip/scala2.13 by @jerryz123 in #1392
- Bump SBT to 1.8.2 by @abejgonzalez in #1446
- Support AL2 manager instances by @abejgonzalez in #1460
- AL2 Auto-Setup NICE DCV by @abejgonzalez in #1468
- Expand TracerV to support more than 7 IPC by @sifive-benjamin-morse in #1383
Changed
- Expose frequency in the builddcp script by @russell-horvath in #1229
- Match field order in channel info by @nandor in #1264
- Localize Java temp directory + Revert to using
sbt-launch.jar
by @abejgonzalez in #1257 - build setup: make env.sh sourcable in contexts without conda functions by @davidbiancolin in #1285
- Relaxed restrictions on pipe channel types by @nandor in #1263
- Move XDC circuit paths to config by @fabianschuiki in #1308
- Moved chipyard tests to main FireSim repository by @nandor in #1314
- Rewrite MIDAS tests by @nandor in #1327
- Eliminate virtual inheritance and simplify tests by @nandor in #1323
- Remove references to buildafi; replace with buildbitstream by @davidbiancolin in #1287
- Move termination to Run Farm
Inst
+monitor_jobs
small rework by @abejgonzalez in #1322 - Provided tests with their own random number generator by @nandor in #1338
- Moved MMIO struct type definitions to headers by @nandor in #1331
- Moved widget logic to individual classes by @nandor in #1339
- Switch VCS simulation over to DPI by @nandor in #1332
- Introduced a uniform harness over bridge tests by @nandor in #1336
- Separated testing from peek-poke logic by @nandor in #1341
- VCS and Verilator DPI switchover by @nandor in #1348
- Improve the names of synchronisation primitives in
simif_emul
by @nandor in #1364 - Replace AXI4 configuration with structures by @nandor in #1358
- Split TutorialSuite into multiple files and helpers by @nandor in #1355
- Introduced a uniform harness across all simulations by @nandor in #1342
- Moved constructor macros to the constructor header by @nandor in #1359
- Eliminate random number generation from simif by @nandor in #1367
- Split
target-agnostic.mk
into multiple files by @nandor in #1353 - Stream Engine IO interfaces by @nandor in #1366
- Split timing functions from simif.h by @nandor in #1371
- Split
simulation_t
from simif.h by @nandor in #1372 - [library] Re-organised library file structure by @nandor in #1361
- Remove the use of DPI utilities from dpi.cc by @nandor in #1379
- Separate XSIM from f1 into
simif_xsim
by @nandor in #1374 - Split project
Makefrag
into multiple components by @nandor in #1354 - Cache the classpath between SBT runs by @nandor in #1390
- Enable clang-tidy on C++ sources by @nandor in #1400
- Moved simulation step control to the PeekPoke bridge by @nandor in #1399
- [library] Introduced a unique main to the simulation. by @nandor in #1368
- Passed memory region offsets to genHeader by @nandor in #1416
- Removed the compiler-generated runtime config by @nandor in #1422
- Re-enabled timeout detection for harnesses by @nandor in #1423
- Moved non-host IF functions from
simif_t
intosimulation_t
by @nandor in #1424 - Restored the runtime config generation phase by @nandor in #1425
- Remove
constructor.h
and replace it with a Scala-generated header by @nandor in #1398 - Enabled scalafmt on more sources by @nandor in #1429
- VCS post-synthesis RTL simulators by @nandor in #1438
- Extended tests to work with post-synth RTL by @nandor in #1439
- Converted FASEDMemoryTimingModel into a bridge by @nandor in #1440
- Move bridge init/finish handling into the simulation base by @nandor in #1441
- Removed
test_harness_bridge
and simplified harnesses by @nandor in #1442 - Bump Conda to 22.11.1-4 by @abejgonzalez in #1481
- New Local FPGA Tutorial by @abejgonzalez in #1453
- FPGA-managed bridge stream support in metasimulation by @davidbiancolin in #1181
- Setup defaults to be single-node by @abejgonzalez in #1260
- Changed "firesim infrasetup" to deploy using a tarball. by @sifive-benjamin-morse in #1299
- Switch to py script for XRT shell flashing by @abejgonzalez in #1385
- Update Vitis docs | Bump FPGA platform to 2022.1 by @abejgonzalez in #1397
- Force using 2022.1 Vitis by @abejgonzalez in #1410
- Localize
.ivy2
and.sbt
folders to FireSim repo by @abejgonzalez in #1456 - Unpin most conda reqs now that we have a lockfile by @abejgonzalez in https://github.com/firesim/...
FireSim 1.15.2 Release
Fix machine-launch-script.sh.
Changed
- Fixed machine-launch-script.sh.
FireSim 1.15.1 Release
Fixes to metasimulation, TracerV, and improved cross-platform support.
Added
- sourceme-f1-manager.sh now has a --skip-ssh-setup argument for users who have pre-set ssh-agent config #1266
Changed
- Instance liveness check now checks to see if login shell is reasonable #1266
- Driver/Metasim build at runtime now executed via run() to avoid conda warnings #1266
- Setup for QCOW2 on a run farm is only performed if the simulation needs it #1266
- The sim launch command is now written to a file before being executed for easier debugging. #1266
Fixed
FireSim 1.15.0 Release
Full migration to Conda-based environment/dependency management; Chipyard now also uses Conda. Bump Rocket Chip/Chisel/etc. Various bugfixes/feature improvements.
Added
- Refactor Conda + Bump Chipyard (which now uses Conda) #1206
- Support FPGA-managed AXI4/DMA in metasimulation #1191
Changed
- Bump chipyard to 1.8.0 #1239
- Bump Rocketchip/chipyard/chisel #1216
- Metasimulation: remove dramsim2 and copy host memory model sources in-tree #1197
- Metasimulation: remove dependency on fesvr for ucontext #1196
- bridges: Remove references to DMA_X in driver sources #1184
- refactor most of machine-launch-script.sh into build-setup.sh #1180
- Backports go to stable branch, which should generally point to the la… #1176
- obey umask and default group in results-workload #1163
- Use libelf and libdwarf from conda #1160
- Improve fabric logging #1159
- Bump to Verilator 4.224 #1156
- ci: support running under forks of firesim #1144
- Allowed bridge parameters to be serialized #1141
- Don't use tsnyder conda channel in production machine-launch-script.sh #1121
- Make bug report system info copy pastable #1104
Fixed
- manager: Cast AWS IDs to string in shareagfi #1227
- Stable backport of 1.12.1 AMI bump #1188
- Fix various VCS metasimulation breakages #1177
- Change elfutils submodule URL to HTTPS #1153
- Annotate Printf statements instead of intercepting parameters. #1151
- Deinit Chipyard's FireSim submodule under FireSim-as-top #1146
- add config_build_recipes.yaml to run_yamls pytest fixture #1143
- Fix mount files ownership #1137
- Add warn_only to vivado builds + Postpone error until all builds complete #1130
- Added missing return in tracerv_t::process_tokens to fix undefined behavior #1129
- correct doc for autocounter_csv_format #1126
- Fixing instructions for external SSH into simulation #1119
- docs: fix underlining in metasimulation configuration section #1106
- Fixed shebang in build-libdwarf.sh and build-libelf.sh scripts (copy #1101) #1105
- VitisShell: Use XPM xpm_cdc_sync_rst for reset synchronizer #1100
Removed
FireSim 1.14.2 Release
Bump to use AWS FPGA Developer AMI 1.12.1 as 1.11.1 has been de-listed. This also bumps Vivado to 2021.2.
Fixed
- Bump to use AWS FPGA Developer AMI 1.12.1
- Bump Vivado to 2021.2
FireSim 1.14.1 Release
Adds firesim builddriver command, various bugfixes.
Added
- New firesim builddriver command, which runs required driver/metasimulation builds without a launched run farm #1114
- Support for Sydney region on AWS #1111
Changed
- Docs cleanup #1114 #1106
- Don't use tsnyder conda channel in production machine-launch-script.sh #1121
Fixed
- Fixed documentation for SSH-ing into simulations of target designs with NICs #1119. Fixes #580.
- VitisShell: Use XPM xpm_cdc_sync_rst for reset synchronizer #1100
- Fix manager xclbin lookup bug during metasimulation #1114, https://groups.google.com/g/firesim/c/VxHX7QkKJCM
FireSim 1.14.0 Release
Introduces support for local (on-premises) FPGAs and distributed metasimulation
Added
- Support for Vitis FPGAs #1087
- Manager support for deploying verilator/vcs metasimulations, plusarg passthrough, and some useful DRYing-out #1076
- ("Where to Run") Initial support running on different run farm hosts #1028
- A host-portable AutoILA transform that instantiates the black box in IR #1059
- Scala Source Formatting via Scalafmt #1060
- VSCode Integration for Scala Development #1056
- Support A Resource-Minimizing strategy ("AREA") for AWS-FPGA #1055
- XDC-Driven Memory Hints for Xilinx FPGAs #1021
- ("what-to-build") Modularize different run platforms (i.e. bitstream builds) #853
- .ini to .yaml config files + supporting different build hosts #1006
- Capture packet dump from switch #1011
Changed
- Cleanup config initialization #1082
- Switch buildfarm API to be similar to runfarm API #1070
- ("Where to Run") Initial support running on different run farm hosts #1028
- Move C++ implementation of bridge streams out of bridge drivers #1017
- awstools typing + small organization #1037
- Collect Bridge Stream RTL Implementation under StreamEngine module #996
- Use conda for distribution-agnostic dependency management #986
- .ini to .yaml config files + supporting different build hosts #1006
- Use FIRRTL 'FPGA backend' passes in the GG compiler + Isolate Emitter #981
Fixed
- Allow argument passing to bit builder #1046
- Move sim. data class arg parsing into classes #1078
- Hide blowfish deprecation warning until 2022-08-31 #1079
- Have yes/no resolve to bool in Yaml #1069
- Add bash-completion and install argcomplete global into it #1041
- Fix CI FPGA sim timeout issue + Use Python3 formatting in run_linux_poweroff CI script #1040
- Revert the change from #842 that makes launchrunfarm block on instances passing status checks #1003
- Fix first clone setup fast script #990
- Update libdwarf submodule url #988
- Update test_amis.json #982