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DMI bridge integration #1657

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DMI bridge integration #1657

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abejgonzalez
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@abejgonzalez abejgonzalez commented Oct 10, 2023 •
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This adds a DMI bridge and associated collateral. Currently, it doesn't batch DMI requests nor does it support loadmem.

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Verilog / AGFI Compatibility

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  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
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@abejgonzalez abejgonzalez self-assigned this Oct 10, 2023
@abejgonzalez abejgonzalez added the changelog:added Put PR title in 'Added' section of changelog label Oct 10, 2023
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Needs ucb-bar/chipyard#1619

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Confirmed to boot Linux (albeit very very slowly).

@abejgonzalez abejgonzalez changed the title [DONOTMERGE] DMIBridge DMI bridge integration Oct 14, 2023
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Ping @sagark @jerryz123

jerryz123
jerryz123 reviewed Nov 2, 2023
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sim/firesim-lib/src/main/scala/bridges/DMIBridge.scala
/**
* Class which parameterizes the DMIBridge
*
* memoryRegionNameOpt, if unset, indicates that firesim-fesvr should not attempt to write a payload into DRAM through the loadmem unit.
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Perhaps add a comment here that DMI+LoadMem is unsupported currently?

jerryz123
jerryz123 approved these changes Nov 2, 2023
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This looks good to me... but I'm not familiar with the bridge APIs enough to judge.

How does this deal with situations when both a TSIBridge and DMIBridge are built?

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@jerryz123 jerryz123 jerryz123 approved these changes

@sagark sagark Awaiting requested review from sagark

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