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Add minimal configs with block device / fased #1370

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@t14916 t14916 commented Jan 6, 2023

Dependent on following chipyard PR:
ucb-bar/chipyard#1302
Adds some minimal FireSim configs to test simulation environment with bridges stripped out.

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Verilog / AGFI Compatibility

Contributor Checklist

  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you add Scaladoc/docstring/doxygen to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous prints/debugging code?
  • Did you state the UI / API impact?
  • Did you specify the Verilog / AGFI compatibility impact?
  • If applicable, did you regenerate and publicly share default AGFIs?
  • If applicable, did you apply the ci:fpga-deploy label?
  • If applicable, did you apply the Please Backport label?

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  • Is the title suitable for inclusion in the changelog and does the PR have a changelog:<topic> label?
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@t14916 t14916 added the changelog:omit Do not include this PR in the changelog label Jan 6, 2023
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