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firesim · Apr 1, 2024 · 52b0f8f · 52b0f8f
1 parent 160220a
commit 52b0f8f
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/platforms/xilinx_alveo_u250/cl_firesim/design/overall_fpga_top.v b/platforms/xilinx_alveo_u250/cl_firesim/design/overall_fpga_top.v
@@ -31,14 +31,14 @@ module overall_fpga_top(
     `define AMBA_AXI_CACHE
     `define AMBA_AXI_PROT
     `define AMBA_AXI_ID
-    `AMBA_AXI_SLAVE_PORT(PCIE_M_AXI, 4, 64, 512)
+    `AMBA_AXI_WIRE(PCIE_M_AXI, 4, 64, 512)
     `undef AMBA_AXI4
     `undef AMBA_AXI_CACHE
     `undef AMBA_AXI_PROT
     `undef AMBA_AXI_ID
 
     `define AMBA_AXI_PROT
-    `AMBA_AXI_SLAVE_PORT(PCIE_M_AXI_LITE, unused, 32, 32)
+    `AMBA_AXI_WIRE(PCIE_M_AXI_LITE, unused, 32, 32)
     `undef AMBA_AXI_PROT
 
     `define AMBA_AXI4