Add Verilog macro helpers to reduce duplication #70
Job | Run time |
---|---|
7s | |
3s | |
4s | |
2s | |
1m 8s | |
1m 13s | |
1m 55s | |
1m 48s | |
7m 19s | |
7m 17s | |
0s | |
0s | |
3h 50m 38s | |
3h 48m 22s | |
11s | |
11s | |
14m 35s | |
14m 39s | |
0s | |
0s | |
9s | |
10s | |
8h 29m 51s |
Job | Run time |
---|---|
7s | |
3s | |
4s | |
2s | |
1m 8s | |
1m 13s | |
1m 55s | |
1m 48s | |
7m 19s | |
7m 17s | |
0s | |
0s | |
3h 50m 38s | |
3h 48m 22s | |
11s | |
11s | |
14m 35s | |
14m 39s | |
0s | |
0s | |
9s | |
10s | |
8h 29m 51s |