ring_oscillator

Parameterized ring oscillator design in verilog. A simple testbench is developed using SystemVerilog. The test is performed by comparing measured and expected frequency computed using the equation: f= 1/(2tn). where n= number of stage of inverter and t= delay of a single inverter.

Project Structure

This project is organized in following manner,
ring_oscillator
  |
  |->   doc : contains project documents like testcase plan, verification plan etc.
          |->   ring_osc_testcase_plan.docx
  |->   rtl : contains rtl code of ring oscillator
          |->   verilog : contains verilog code of Ring Oscillator
                   |-> ring_oscillator.v
  |->   scripts : contains scripts for running tests.
          |-> runscript.ps1 : script for ruuning tests with Questasim or modelsim on windows
  |->   sim : contains simulation work directory. This is where you should open a terminal to run your tests.
  |->   spec : contains RTL design specification.
          |->   ring_oscillator_design.docx
  |->   tb: Contains Simple SystemVerilog testbench files.
          |->   ring_osc_defines.sv
          |->   simple_tb.sv

Run Instruction

Running Single Test without coverage analysis

> cd sim
> ..\scripts\runscript.ps1