Fixes exceptions resulting from using SPI0Command #9140
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…perations such as: Write Status Register-1, Sector Eraser, etc. Moved PRECACHE_END to ensure `Wait_SPI_Idlep` and `xt_wsr_ps` are included in the iCache. Added SPIUCSSETUP to give more settling time for #CS.
and the "target opcode". They are now tightly coupled. Update flash quirks.
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Let's put this on hold. I need to look closer at the sequence of calls used when doing write enabled by other examples. Some examples poll the status register until bit WEL is set before continuing. |
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Resolves exceptions occurring when using
experimental::SPI0Commandfor flash write operations such as: Write Status Register-1, Sector Eraser, etc.Moved PRECACHE_END to ensure
Wait_SPI_Idlepandxt_wsr_psare included in the iCache.Added SPIUCSSETUP to give more settling time for #CS.