Add plugin to generate multiple design clocks

toolflow/vivado/common/common.tcl

@@ -674,4 +674,95 @@ namespace eval tapasco {
   proc is_versal {} {
     return [string match "versal*" [get_property FAMILY [get_parts -of_objects [current_project]]]]
   }
+
+
+  proc create_clocks_ultrascale {name num_clocks freqs} {
+    set group [create_bd_cell -type hier $name]
+    set instance [current_bd_instance .]
+    current_bd_instance $group
+    set full_wizards [expr $num_clocks / 7]
+    set remaining [expr $num_clocks % 7]
+
+    set clk_in [create_bd_pin -type "clk" -dir "I" "clk_in"]
+    set resetn [create_bd_pin -type "rst" -dir "I" "resetn"]
+    set locked [create_bd_pin -dir "O" "locked"]
+
+    set const1 [tapasco::ip::create_constant const1 1 1]
+    set locked_acc [get_bd_pins $const1/dout]
+
+    for {set i 0} {$i < $full_wizards} {incr i} {
+      set clk_wiz [tapasco::ip::create_clk_wiz clk_wiz_$i]
+      set base_idx [expr $i * 7]
+      set_property -dict [list \
+        CONFIG.USE_SAFE_CLOCK_STARTUP {false} \
+        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + 0]] \
+        CONFIG.CLKOUT2_USED {true} \
+        CONFIG.CLKOUT2_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + 1]] \
+        CONFIG.CLKOUT3_USED {true} \
+        CONFIG.CLKOUT3_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + 2]] \
+        CONFIG.CLKOUT4_USED {true} \
+        CONFIG.CLKOUT4_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + 3]] \
+        CONFIG.CLKOUT5_USED {true} \
+        CONFIG.CLKOUT5_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + 4]] \
+        CONFIG.CLKOUT6_USED {true} \
+        CONFIG.CLKOUT6_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + 5]] \
+        CONFIG.CLKOUT7_USED {true} \
+        CONFIG.CLKOUT7_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + 6]] \
+        CONFIG.NUM_OUT_CLKS {7} \
+        CONFIG.USE_LOCKED {true} \
+        CONFIG.USE_RESET {true} \
+        CONFIG.RESET_TYPE {ACTIVE_LOW} \
+        CONFIG.RESET_PORT {resetn} \
+        CONFIG.PRIM_SOURCE {No_buffer} \
+      ] $clk_wiz
+      connect_bd_net $clk_in [get_bd_pins $clk_wiz/clk_in1]
+      connect_bd_net $resetn [get_bd_pins $clk_wiz/resetn]
+      for {set j 1} {$j <= 7} {incr j} {
+        set k [expr $base_idx + $j]
+        set clk_out [create_bd_pin -type "clk" -dir "O" clk_out$k]
+        connect_bd_net [get_bd_pins $clk_wiz/clk_out$j] $clk_out
+      }
+      set locked_and [tapasco::ip::create_logic_vector locked_and$i]
+      set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {and} CONFIG.LOGO_FILE {data/sym_andgate.png}] $locked_and
+      connect_bd_net $locked_acc [get_bd_pins $locked_and/Op1]
+      connect_bd_net [get_bd_pins $clk_wiz/locked] [get_bd_pins $locked_and/Op2]
+      set locked_acc [get_bd_pins $locked_and/Res]
+    }
+
+    if {$remaining != 0} {
+      set clk_wiz [tapasco::ip::create_clk_wiz clk_wiz_$i]
+      set base_idx [expr $full_wizards * 7]
+      set wizard_properties [list \
+        CONFIG.USE_SAFE_CLOCK_STARTUP {false} \
+        CONFIG.NUM_OUT_CLKS $remaining \
+        CONFIG.USE_LOCKED {true} \
+        CONFIG.USE_RESET {true} \
+        CONFIG.RESET_TYPE {ACTIVE_LOW} \
+        CONFIG.RESET_PORT {resetn} \
+        CONFIG.PRIM_SOURCE {No_buffer} \
+      ]
+      for {set i 1} {$i <= $remaining} {incr i} {
+        lappend wizard_properties \
+          CONFIG.CLKOUT${i}_REQUESTED_OUT_FREQ [lindex $freqs [expr $base_idx + $i - 1]] \
+          CONFIG.CLKOUT${i}_USED {true} \
+      }
+      set_property -dict $wizard_properties $clk_wiz
+      connect_bd_net $clk_in [get_bd_pins $clk_wiz/clk_in1]
+      connect_bd_net $resetn [get_bd_pins $clk_wiz/resetn]
+      for {set i 1} {$i <= $remaining} {incr i} {
+        set j [expr $base_idx + $i]
+        set clk_out [create_bd_pin -type "clk" -dir "O" clk_out$j]
+        connect_bd_net [get_bd_pins $clk_wiz/clk_out$i] $clk_out
+      }
+      set locked_and [tapasco::ip::create_logic_vector locked_and]
+      set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {and} CONFIG.LOGO_FILE {data/sym_andgate.png}] $locked_and
+      connect_bd_net $locked_acc [get_bd_pins $locked_and/Op1]
+      connect_bd_net [get_bd_pins $clk_wiz/locked] [get_bd_pins $locked_and/Op2]
+      set locked_acc [get_bd_pins $locked_and/Res]
+    }
+
+    connect_bd_net $locked_acc $locked
+
+    current_bd_instance $instance
+  }
 }

toolflow/vivado/platform/AU280/AU280.tcl

@@ -26,6 +26,11 @@ namespace eval platform {
     exit 1
   }
 
+  proc get_platform_name {} {
+    return "AU280"
+  }
+
+
   source $::env(TAPASCO_HOME_TCL)/platform/pcie/pcie_base.tcl
 
   if {[tapasco::is_feature_enabled "HBM"]} {

toolflow/vivado/platform/AU280/board.xdc

@@ -37,6 +37,10 @@ set_property PACKAGE_PIN D32 [get_ports {dout_0[0]}]
 set_property IOSTANDARD LVCMOS18 [get_ports {dout_0[0]}]
 
 create_pblock pblock_axi_pcie
-resize_pblock pblock_axi_pcie -add SLR0
+add_cells_to_pblock [get_pblocks pblock_axi_pcie] [get_cells -quiet [list system_i/host/axi_pcie3_0]]
+add_cells_to_pblock [get_pblocks pblock_axi_pcie] [get_cells -quiet [list system_i/host/in_ic]]
+resize_pblock [get_pblocks pblock_axi_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X7Y3}
 set_property IS_SOFT TRUE [get_pblocks pblock_axi_pcie]
-add_cells_to_pblock pblock_axi_pcie [get_cells [list system_i/host/axi_pcie3_0]]
+
+
+

toolflow/vivado/platform/aws/aws.tcl

@@ -58,6 +58,13 @@ namespace eval platform {
   proc get_pe_base_address {} {
     return 0x20000
   }
+
+
+
+  proc get_platform_name {} {
+    return "aws"
+  }
+
   # end mandatory functions
 
   proc get_address_map {{pe_base ""}} {
@@ -100,6 +107,15 @@ namespace eval platform {
     return $peam
   }
 
+  proc get_ignored_segments { } {
+    set ignored [list]
+  # lappend ignored "/host/f1_inst/S_AXI_DDRA/Mem_DDRA"
+    lappend ignored "/host/f1_inst/S_AXI_DDRB/Mem_DDRB"
+    lappend ignored "/host/f1_inst/S_AXI_DDRC/Mem_DDRC"
+    lappend ignored "/host/f1_inst/S_AXI_DDRD/Mem_DDRD"
+    return $ignored
+  }
+
   proc create_subsystem_intc {} {
 
     set s_axi [create_bd_intf_pin -mode Slave -vlnv [tapasco::ip::get_vlnv "aximm_intf"] "S_INTC"]
@@ -309,7 +325,7 @@ namespace eval platform {
     set clkwiz_design_aclk [create_bd_pin -type "clk" -dir "O" "design_aclk"]
     set clkwiz_design_aresetn [create_bd_pin -type "rst" -dir "O" "design_aresetn"]
 
-    if {[info exist clk_group] eq 0} {
+    #if {[info exist clk_group] eq 0} {
       set design_clk_wiz [tapasco::ip::create_clk_wiz design_clk_wiz]
       set_property -dict [list \
         {CONFIG.CLK_OUT1_PORT} {design_clk} \
@@ -331,22 +347,22 @@ namespace eval platform {
       # connect external design clk
       connect_bd_net [get_bd_pins -of_objects $design_clk_wiz -filter {NAME == "design_clk"}] $clkwiz_design_aclk
       connect_bd_net [get_bd_pins -of_objects $design_clk_wiz -filter {NAME == "locked"}] $clkwiz_design_aresetn
-    } else {
-      set_property -dict [list \
-        "CONFIG.NUM_[string toupper $clk_group]_CLOCKS" [expr "$clk_port + 1"] \
-        {CONFIG.CLOCK_B_RECIPE} {2} \
-        {CONFIG.CLOCK_C_RECIPE} {1} \
-      ] $f1_inst
-
-      if {$clk_group == "a" && $clk_port == "0"} {
-        connect_bd_net [get_bd_pins -of_objects $f1_inst -filter {NAME == "clk_main_a0_out"}] $clkwiz_design_aclk
-      } else {
-        connect_bd_net \
-          [get_bd_pins -of_objects $f1_inst -filter "NAME == clk_extra_${clk_group}${clk_port}_out"] \
-          $clkwiz_design_aclk
-      }
-      connect_bd_net [get_bd_pins -of_objects $f1_inst -filter {NAME == "rst_main_n_out"}] $clkwiz_design_aresetn
-    }
+    # } else {
+    #   set_property -dict [list \
+    #     "CONFIG.NUM_[string toupper $clk_group]_CLOCKS" [expr "$clk_port + 1"] \
+    #     {CONFIG.CLOCK_B_RECIPE} {2} \
+    #     {CONFIG.CLOCK_C_RECIPE} {1} \
+    #   ] $f1_inst
+
+    #   if {$clk_group == "a" && $clk_port == "0"} {
+    #     connect_bd_net [get_bd_pins -of_objects $f1_inst -filter {NAME == "clk_main_a0_out"}] $clkwiz_design_aclk
+    #   } else {
+    #     connect_bd_net \
+    #       [get_bd_pins -of_objects $f1_inst -filter "NAME == clk_extra_${clk_group}${clk_port}_out"] \
+    #       $clkwiz_design_aclk
+    #   }
+    #   connect_bd_net [get_bd_pins -of_objects $f1_inst -filter {NAME == "rst_main_n_out"}] $clkwiz_design_aresetn
+    # }
 
     # DDR training status
     set ddr_ready [create_bd_pin -type "undef" -dir O "ddr_ready"]
@@ -375,22 +391,22 @@ namespace eval platform {
     # connect_bd_net [tapasco::subsystem::get_port "design" "clk"] [get_bd_pins $ddr_ic/aclk1]
     # connect_bd_net [tapasco::subsystem::get_port "host" "clk"] [get_bd_pins $ddr_ic/aclk]
 
-    set ddr_ic [tapasco::ip::create_axi_ic "ddr_ic" 2 [llength $ddr_available]]
+    set ddr_ic [tapasco::ip::create_axi_sc "ddr_ic" 2 [llength $ddr_available] 2]
+    set_property -dict [list \
+      CONFIG.HAS_ARESETN {1}
+    ] $ddr_ic
+
 
     connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "ACLK"}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S00_* && TYPE == clk}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ M* && TYPE == clk}]
+      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "aclk"}]
 
     connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S01_* && TYPE == clk}]
+      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "aclk1"}]
 
     connect_bd_net [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "ARESETN"}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S00* && TYPE == rst}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ M* && TYPE == rst}]
+      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "aresetn"}]
 
-    connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
+    #connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
       [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S01_* && TYPE == rst}]
 
     set num_ddr 0
@@ -424,10 +440,13 @@ namespace eval platform {
 
     # connect_bd_intf_net [get_bd_intf_pins "$out_ic/S00_AXI"] [get_bd_intf_pins "$f1_inst/M_AXI_OCL"]
 
-    set out_ic [tapasco::ip::create_axi_ic "out_ic" 1 5]
+    set out_ic [tapasco::ip::create_axi_sc "out_ic" 1 5 2]
+    set_property -dict [list \
+      CONFIG.HAS_ARESETN {1}
+    ] $out_ic
 
     # Without this, Vivado chooses wrong parameters (at least in 2018.3)
-    set_property -dict [list \
+    #set_property -dict [list \
       {CONFIG.ENABLE_ADVANCED_OPTIONS} {1} \
       {CONFIG.XBAR_DATA_WIDTH} {32} \
     ] $out_ic
@@ -439,6 +458,8 @@ namespace eval platform {
     connect_bd_intf_net [get_bd_intf_pins -of_objects $out_ic -filter {NAME == M04_AXI}] $m_mem_gpio
 
     connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
+      [get_bd_pins -of_objects $out_ic -filter {NAME == "aclk"}]
+    #connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
       [get_bd_pins -of_objects $out_ic -filter {NAME == ACLK}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == clk}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == clk}] \
@@ -447,24 +468,29 @@ namespace eval platform {
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M04_* && TYPE == clk}]
 
     connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
+      [get_bd_pins -of_objects $out_ic -filter {NAME == "aclk1"}]
+    #connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == clk}]
 
     connect_bd_net [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"] \
-      [get_bd_pins -of_objects $out_ic -filter {NAME == ARESETN}] \
-      [get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == rst}] \
+      [get_bd_pins -of_objects $out_ic -filter {NAME == "aresetn"}]
+      #[get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M02_* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M04_* && TYPE == rst}]
 
-    connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
+    #connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == rst}]
 
     connect_bd_intf_net [get_bd_intf_pins -of_objects $f1_inst -filter {NAME == "M_AXI_OCL"}] \
       [get_bd_intf_pins -of_objects $out_ic -filter {NAME == "S00_AXI"}]
 
     # Connect "in" AXI ports
-    set in_ic [tapasco::ip::create_axi_ic "in_ic" 1 1]
+    set in_ic [tapasco::ip::create_axi_sc "in_ic" 1 1]
+    set_property -dict [list \
+      CONFIG.HAS_ARESETN {1}
+    ] $in_ic
 
     connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
       [get_bd_pins -of_objects $in_ic -filter {TYPE == clk}]

toolflow/vivado/platform/common/platform.tcl

@@ -85,6 +85,7 @@ namespace eval platform {
 
     wire_subsystem_wires
     wire_subsystem_intfs
+    tapasco::call_plugins "post-wiring"
     addressmap::construct_address_map
 
     save_bd_design
@@ -315,4 +316,12 @@ namespace eval platform {
     puts "Platform does not specify any ignored segments."
     return $ignored
   }
+
+  proc create_clocks {name num_clocks freqs} {
+    error "Platform does not implement mandatory proc create_clocking_wizard!"
+  }
+
+  proc get_platform_name {} {
+    error "Platform does not implement mandatory proc get_platform_name!"
+  }
 }