Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Picolib support #9

Open
wants to merge 16 commits into
base: master
Choose a base branch
from
Open

Conversation

tsmk94
Copy link
Contributor

@tsmk94 tsmk94 commented Sep 30, 2020

This adds the picolibc support to the repository. The library is build automatically with a script calling make picolibc. Also software and hardware (controller) implementation is provided to support stdin/stdout with memory buffers. An example is added to show how to use is properly.
Also the controller is now resetted with every write to 0x0.

Add a script to build picolibc by using make picolibc. The script works with riscv32 and riscv64 compilers.
It is installed locally to the repository with a specs-specs file containing all necessary options for correct linking.
Also a dummyfile is included for printf support which needs to be adjusted in future commits.
Include the build of our __iob implementation for printf support in the meson build of picolibc
Adjust clean target of Makefile
Move sections containing function pointers (and not code as I initially thought) to the data memory as well. Otherwise the start up code cannot load these pointers from memory.
RVController contains now all required registers for the picolibc support and interrupt is set after grace period.
Add implementation of putc and getc operations on stdin/stdout. In initialization phase base addresses of the RAM buffers are fetched. One buffer is used to write stdout output and one for "reading" from stdin.
The Controller resets the RISC-V core now with every write of '1' to the start register at 0x0, no matter in which state it is currently. This is required for proper support of the cores' debug modules.
Add an example using the picolibc with software and makefiles for both host and PE.
Delay core reset after interrupt by four cycles to avoid reset directly with new write request of Pico since this will cause that the Pico cannot be resetted properly and will hang-up in a second execution.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

1 participant