Issues: enjoy-digital/litex
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Trying to interact with UART via Rust binary (stuck at liftoff)
#1935
opened Apr 20, 2024 by
roby2014
default FIFO depth for video is too large for some devices
#1931
opened Apr 18, 2024 by
suarezvictor
Native windows Vivado and WSL2 Litex build fails to find toolchain
#1930
opened Apr 17, 2024 by
exitrip
Add example for embedding a LiteX SOC into Vivado project for Zynq
#1910
opened Mar 29, 2024 by
benfre
Xilinx Zynq-7000 digilent_zedboard: workflow failed with meson ERROR: No statements in code.
#1889
opened Feb 14, 2024 by
ZhanYF
Clock domain crossing for peripherals
help-welcome :)
new-feature
sponsor-welcome :)
#1873
opened Jan 11, 2024 by
rhgndf
[Feature request] Support of pmem / Non Volatile Memory
help-welcome :)
new-feature
sponsor-welcome :)
#1870
opened Jan 6, 2024 by
ohault
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