SingleCycle-ARM-CPU-Simple-Implementation

A very simple implementation of a single cycle 32bit ARM CPU with a fairly reduced instruction set.

Instruction Set

31:28	27:26	25:20	19:16	15:12	11:0
xxxx	00	x cmd x	Rn	Rd	xxxxxxxx Rm

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALU.v		ALU.v
Adder.v		Adder.v
Controller.v		Controller.v
DataMemory.v		DataMemory.v
Datapath.bdf		Datapath.bdf
ImmediateExtender.v		ImmediateExtender.v
InstructionMemory.v		InstructionMemory.v
README.md		README.md
SingleCycle.v		SingleCycle.v
SingleCycle_tb.v		SingleCycle_tb.v
SingleCycle_tv.tv		SingleCycle_tv.tv
instrucitons.tv		instrucitons.tv
memory.tv		memory.tv
reg_with_sync_res.v		reg_with_sync_res.v
regfile.v		regfile.v
shifter.v		shifter.v
simpleAdder.v		simpleAdder.v
two_to_one_mux.v		two_to_one_mux.v