ELEC374

The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O. This project was created for an academic course at Queen's University. Please feel free to look at our work, but do not copy it directly, especially if you are taking this course.

MIT License

Copyright [2021] [Sydney Caulfeild, Varnikaa Gupta, Emma Paczkowski]

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

Name		Name	Last commit message	Last commit date
Latest commit History 101 Commits
db		db
CPUproject.v		CPUproject.v
IncPC_32_bit.v		IncPC_32_bit.v
README.md		README.md
add_32_bit.v		add_32_bit.v
add_tb.v		add_tb.v
addi_tb.v		addi_tb.v
alu.v		alu.v
and_32_bit.v		and_32_bit.v
and_tb.v		and_tb.v
andi_tb.v		andi_tb.v
branch.v		branch.v
conff_logic.v		conff_logic.v
control_unit.v		control_unit.v
decoder_2_to_4.v		decoder_2_to_4.v
decoder_4_to_16.v		decoder_4_to_16.v
design_decisions.md		design_decisions.md
div_32_bit.v		div_32_bit.v
div_tb.v		div_tb.v
encoder_32_to_5.v		encoder_32_to_5.v
ff_logic.v		ff_logic.v
in_tb.v		in_tb.v
init.mif		init.mif
jal_tb.v		jal_tb.v
jr_tb.v		jr_tb.v
ld_tb.v		ld_tb.v
ldi_tb.v		ldi_tb.v
mar_unit.v		mar_unit.v
memoryRam.v		memoryRam.v
memoryRam_bb.v		memoryRam_bb.v
memoryRam_inst.v		memoryRam_inst.v
memram.v		memram.v
memram_inst.v		memram_inst.v
mfhi_tb.v		mfhi_tb.v
mflo_tb.v		mflo_tb.v
mul_32_bit.v		mul_32_bit.v
mul_tb.v		mul_tb.v
mux_2_to_1.v		mux_2_to_1.v
mux_32_to_1.v		mux_32_to_1.v
mux_3_to_1.v		mux_3_to_1.v
negate_32_bit.v		negate_32_bit.v
negate_tb.v		negate_tb.v
not_32_bit.v		not_32_bit.v
not_tb.v		not_tb.v
or_32_bit.v		or_32_bit.v
or_tb.v		or_tb.v
ori_tb.v		ori_tb.v
out_tb.v		out_tb.v
phase3_tb.v		phase3_tb.v
ram.v		ram.v
reg_32_bits.v		reg_32_bits.v
rol_32_bit.v		rol_32_bit.v
rol_tb.v		rol_tb.v
ror_32_bit.v		ror_32_bit.v
ror_tb.v		ror_tb.v
select_encode_logic.v		select_encode_logic.v
shl_32_bit.v		shl_32_bit.v
shl_tb.v		shl_tb.v
shr_32_bit.v		shr_32_bit.v
shr_tb.v		shr_tb.v
st_tb.v		st_tb.v
sti_tb.v		sti_tb.v
sub_32_bit.v		sub_32_bit.v
sub_tb.v		sub_tb.v

emmapaczkowski/ELEC374

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