Fix uart::flush with FIFO at Half-Duplex mode

[qwerty19106]

CC #2875

The problem (STM32G030C8, usart_v4, FIFO always enabled)

I make Uart with Half-Duplex mode, write ~16 bytes, then call blocking_flush, then call read_until_idle. No other side, only pull up.
As result I get ~7 last bytes which was sent over uart.write.

I did a little research and found out that the TC flag works correctly. It this is confirmed by tests also.

When the last data is written to the USART_TDR register, wait until TC = 1.
–When FIFO mode is disabled, this indicates that the transmission of the last frame
is complete.
–When FIFO mode is enabled, this indicates that both TXFIFO and shift register are
empty.

Possible it is errate, but I not found it within official errata.

Solution

Now I clear cr1.re flag before write, this solves the problem.

The ideal cycle read-write in Half-Duplex master mode:
write - write - ... - flush - read
Then we can clear cr1.re before write, and set after flush.
But we should call flush before read, but it is impossible with current API.

I propose two variants (only for half-duplex):

1. Add flush to start of read, clear cr1.re before write, and set after flush.
   It requires the real async flush, which I can add some later.
2. Clear cr1.re before write, and set after flush, and set before read.
   It is some not obvious because after flush the some bytes can be read before we call read. But without flush the receiver will be disabled until read.

It implement variant 1 in this PR, and wait any ideas and discussion.

[Dirbaio]

this should be true?

[Dirbaio]

I think with Option 2 you can still receive your own bytes if you do .write(), .read() without a flush, because .read() will reenable the receiver when still transmitting. Perhaps do option 2, but instead make .read() do a flush? so .write(); .read() Just Works even if you don't call flush?

[qwerty19106]

I didn't quite understand your point.
You suggest call flush at the end of write?
Some driver calls write - write - flush - read. In this case the flush will be called between two write.

[Dirbaio]

no. call flush at the start of read. so that write + read works. with the changes in this PR, only write + flush + read works.

[qwerty19106]

Done.
I think the Uart::split method should not be available for Half-Duplex mode. But I not know how do it in current API: it requires particular struct HalfDuplexUart, and it broke BufferedUart.

[Dirbaio]

thank you!