GitHub - eimon96/VHDL

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
DFF.PNG		DFF.PNG
DFF.vhdl		DFF.vhdl
DFF_tb.vhdl		DFF_tb.vhdl
README.md		README.md
TFF.PNG		TFF.PNG
TFF.vhdl		TFF.vhdl
TFF_tb.vhdl		TFF_tb.vhdl
adder16.PNG		adder16.PNG
adder16.vhdl		adder16.vhdl
adder16_tb.vhdl		adder16_tb.vhdl
basic_gates_using_NOR.PNG		basic_gates_using_NOR.PNG
basic_gates_using_NOR.vhdl		basic_gates_using_NOR.vhdl
basic_gates_using_NOR_tb.vhdl		basic_gates_using_NOR_tb.vhdl
dec_2to4.PNG		dec_2to4.PNG
dec_2to4.vhdl		dec_2to4.vhdl
dec_2to4_tb.vhdl		dec_2to4_tb.vhdl
demux_1to2.PNG		demux_1to2.PNG
demux_1to2.vhdl		demux_1to2.vhdl
demux_1to2_tb.vhdl		demux_1to2_tb.vhdl
demux_1to4.PNG		demux_1to4.PNG
demux_1to4.vhdl		demux_1to4.vhdl
demux_1to4_tb.vhdl		demux_1to4_tb.vhdl
implement_basic_gates_using_nand.PNG		implement_basic_gates_using_nand.PNG
implement_basic_gates_using_nand.vhdl		implement_basic_gates_using_nand.vhdl
implement_basic_gates_using_nand_tb.vhdl		implement_basic_gates_using_nand_tb.vhdl
mux_2to1.PNG		mux_2to1.PNG
mux_2to1.vhdl		mux_2to1.vhdl
mux_2to1_tb.vhdl		mux_2to1_tb.vhdl
mux_4to1.PNG		mux_4to1.PNG
mux_4to1.vhdl		mux_4to1.vhdl
mux_4to1_tb.vhdl		mux_4to1_tb.vhdl
testValues.c		testValues.c

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Basic logic gates implementations using

VHDL Simili 3.1 (Symphony EDA Sonata 3.1)

(win64)

Furthermore:

D Flip Flop-schematic:

T Flip Flop-schematic:

https://www.multisim.com/contributors/574827-eimon96/

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vhdl logic-gates vhdl-code vhdl-coursework vhdl-testbench

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