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Fix: slv switch AW channel didn't check wrch FIFO was ready to propag… AXI-CROSSBAR #41: Commit 9b5f325 pushed by dpretet
May 28, 2024 19:03 35m 14s ordering
ordering
May 28, 2024 19:03 35m 14s
Change: Split slave/master switchs into read/write separated modules AXI-CROSSBAR #40: Commit d5e6b20 pushed by dpretet
May 21, 2024 19:37 35m 54s ordering
ordering
May 21, 2024 19:37 35m 54s
Change: Slight doc update AXI-CROSSBAR #39: Commit 39b41e1 pushed by dpretet
May 19, 2024 08:31 36m 7s main
main
May 19, 2024 08:31 36m 7s
New: Add ASIC synthesis flow, run in CI flow AXI-CROSSBAR #38: Commit ec8a0fe pushed by dpretet
May 15, 2024 08:58 36m 53s v1.0.1
v1.0.1
May 15, 2024 08:58 36m 53s
New: Add ASIC synthesis flow, run in CI flow AXI-CROSSBAR #37: Commit ec8a0fe pushed by dpretet
May 15, 2024 08:51 39m 40s main
main
May 15, 2024 08:51 39m 40s
New: Add ASIC synthesis flow, run in CI flow AXI-CROSSBAR #36: Commit ec8a0fe pushed by dpretet
May 14, 2024 13:19 37m 20s cdc_issue
cdc_issue
May 14, 2024 13:19 37m 20s
Fix: Correct clock source for master interface AXI-CROSSBAR #35: Commit c9fbc31 pushed by dpretet
May 12, 2024 15:13 35m 5s cdc_issue
cdc_issue
May 12, 2024 15:13 35m 5s
Chamge: slight doc updates AXI-CROSSBAR #34: Commit d0b8a46 pushed by dpretet
May 12, 2024 15:09 5m 6s cdc_issue
cdc_issue
May 12, 2024 15:09 5m 6s
Chamge: slight doc updates AXI-CROSSBAR #33: Commit d0b8a46 pushed by dpretet
April 24, 2024 19:15 36m 7s main
main
April 24, 2024 19:15 36m 7s
Slight README update AXI-CROSSBAR #32: Commit 1d68410 pushed by dpretet
March 31, 2024 17:16 1h 15m 19s main
main
March 31, 2024 17:16 1h 15m 19s
Change: Remove timeout feature in architecture doc AXI-CROSSBAR #31: Commit aba82fa pushed by dpretet
March 31, 2024 17:07 1h 2m 15s main
main
March 31, 2024 17:07 1h 2m 15s
Change: Remove timeout feature in architecture doc AXI-CROSSBAR #30: Commit d869bd1 pushed by dpretet
March 31, 2024 17:02 1h 2m 42s main
main
March 31, 2024 17:02 1h 2m 42s
slight readme update AXI-CROSSBAR #29: Commit 7477d6a pushed by dpretet
March 30, 2024 20:28 1h 5m 49s main
main
March 30, 2024 20:28 1h 5m 49s
slight readme update AXI-CROSSBAR #28: Commit 54f4a5f pushed by dpretet
March 30, 2024 19:30 1h 4m 15s main
main
March 30, 2024 19:30 1h 4m 15s
slight readme update AXI-CROSSBAR #27: Commit 19660a5 pushed by dpretet
March 30, 2024 19:29 1h 11m 23s main
main
March 30, 2024 19:29 1h 11m 23s
Remove twitter share link AXI-CROSSBAR #26: Commit f11d86b pushed by dpretet
March 30, 2024 19:28 1h 3m 23s main
main
March 30, 2024 19:28 1h 3m 23s
Add IOs/Parameters explanation AXI-CROSSBAR #25: Commit a56430e pushed by dpretet
March 30, 2024 19:23 1h 18m 25s v1.0.0
v1.0.0
March 30, 2024 19:23 1h 18m 25s
Add IOs/Parameters explanation AXI-CROSSBAR #24: Commit a56430e pushed by dpretet
March 30, 2024 19:23 1h 7m 27s main
main
March 30, 2024 19:23 1h 7m 27s
Add IOs/Parameters explanation AXI-CROSSBAR #23: Commit a56430e pushed by dpretet
March 30, 2024 18:11 1h 1m 41s alock_1b
alock_1b
March 30, 2024 18:11 1h 1m 41s
Add IOs/Parameters explanation AXI-CROSSBAR #22: Commit fe7e6ee pushed by dpretet
March 30, 2024 16:37 1h 4m 6s alock_1b
alock_1b
March 30, 2024 16:37 1h 4m 6s
Add IOs/Parameters explanation AXI-CROSSBAR #21: Commit d197c6d pushed by dpretet
March 30, 2024 16:22 1h 14m 1s alock_1b
alock_1b
March 30, 2024 16:22 1h 14m 1s
Add IOs/Parameters explanation AXI-CROSSBAR #20: Commit 7d3af82 pushed by dpretet
March 30, 2024 16:21 1h 4m 35s alock_1b
alock_1b
March 30, 2024 16:21 1h 4m 35s
Add IOs/Parameters explanation AXI-CROSSBAR #19: Commit 53cbc61 pushed by dpretet
March 30, 2024 16:20 1h 1m 36s alock_1b
alock_1b
March 30, 2024 16:20 1h 1m 36s
Change: Resize ALOCK to 1 bit. No more AXI3 capable AXI-CROSSBAR #18: Commit 2ff38a4 pushed by dpretet
March 4, 2024 20:18 1h 9m 30s alock_1b
alock_1b
March 4, 2024 20:18 1h 9m 30s